Recent Advances in GaN‐Based Power HEMT Devices

A new superjunction LDMOS (SJ-LDMOS) is proposed with the step doping buffered layer under the SJ layer to obtain the low loss for the high-voltage region. The substrate-assisted depletion effect, which results from the p-type substrate for the n-channel SJ-LDMOS, has been eliminated by the step doping buffer layer. By the effect of the electric field modulation, a more uniform lateral electric filed is obtained due to the new high-electric field peaks introduced by the buffered step doping, which improves the breakdown voltage (BV) and average lateral electric field. Using ISE simulation, the BV of proposed SJ-LDMOST is increased by $\sim 50$ % than that of the conventional LDMOS, and improved by $\sim 32$ % than that of buffered SJ-LDMOS. The lateral average electric field is increased to 19 V/ $\mu $ m in the high-voltage region The experimental ${R} _{\mathbf {\mathrm{{\scriptstyle ON}},{\textrm sp}}}$ of the proposed SJ-LDMOS is 241 m $\Omega \,\cdot $ $\mathrm{cm}^{\mathrm {\mathbf {2}}}$ with a BV of 368 V, breaking the silicon limit relationship for ${R} _{\mathrm{{\scriptstyle ON}},\textrm {sp}}$ of 71.8 m $\Omega ~\cdot ~\mathrm{cm}^{\mathrm {\mathbf {2}}}$ with the BV of 242 V in the conventional LDMOS with the same drift region length The merit of BV/ $R _{\mathrm{{\scriptstyle ON}},\textrm {sp}}$ is 15.3 for the proposed SJ-LDMOS compared with that of 3.4 for the conventional LDMOS.

New Superjunction LDMOS Breaking Silicon Limit by Electric Field Modulation of Buffered Step Doping

A new lateral power MOSFET structure [folded-accumulation LDMOS (FALDMOS)] is proposed, in which the silicon-substrate surface is trenched to form a folded shape from the channel to the drain electrode and the gate is extended to the drain. The majority-carrier accumulation layer is formed as the device is in on state due to the extended gate in the drift region whose concentration is higher than that in a conventional LDMOS at the same breakdown voltage (BV), resulting from the additional electric-field modulation, and an extra majority carrier is introduced on the sidewall of the trench, which reduced the on-resistance of the drift region further. In addition, the channel density is doubled because of trenching the folded channel, which reduced the channel on-resistance. It indicates by simulation that the specific on-resistance of 4.6 mOmegamiddotmm2 with a BV of 27.4 V in FALDMOS is lower than that of the previously reported lowest one.

Folded-Accumulation LDMOST: New Power MOS Transistor With Very Low Specific On-Resistance

A new solution based on the concept of a deep drain diffusion combined with field plates (FPs) is proposed for the superjunction lateral double diffused MOSFET (SJ-LDMOS) device. The deep drain diffusion suppresses the curvature effect of the conventional SJ-LDMOS and the FPs optimize the electric field distribution further. Simulated results show that the proposed SJ-LDMOS exhibits figure of merits of 12.8 and 8.5 MW/cm $^{\mathrm{{2}}}$ for 700 and 1200 V ratings, respectively, which are about 20% better than the prior art. Moreover, the proposed SJ-LDMOS is less sensitive to the charge imbalance. Using the isotropic etch technique followed by implantation, the deep drain diffusion is easy to be fabricated.

A New Solution for Superjunction Lateral Double Diffused MOSFET by Using Deep Drain Diffusion and Field Plates

In this paper, a new power metal-oxide-semiconductor field-effect transistor (MOSFET) with a FS surface to reduce the specific on-resistance Ron,sp is proposed. Semi-insulating polycrystalline silicon (SIPOS) is deposited over a thin oxide layer. Drift-region concentration is higher in the proposed device than that of conventional lateral double-diffused MOS (LDMOS), and its structure with SIPOS is compared at the same breakdown voltage Bv. In the proposed MOSFET, the effect of electric-field modulation is improved, when compared with an accumulation LDMOS transistor (ALDMOST) due to a complete 3-D reduced surface-field effect. An extra multilayer majority carrier is introduced on the sidewalls of the trench, which reduces Ron,sp of the drift region. This indicates that the ideal silicon limit of the tradeoff of Bv and Ron,sp has been broken due to the lowest Ron,sp value in the proposed MOSFET. In the proposed MOSFET, Ron,sp (i.e., 13.5 mΩ·cm2) and Bv (i.e., 440 V) are improved greatly, when compared with the ALDMOST (i.e., with an Ron,sp of 26 mΩ·cm2 and Bv of 400 V) and a superjunction structure (i.e., with an Ron,sp of 98 mΩ·cm2 and Bv of 410 V).

Low Specific on-Resistance Power MOS Transistor With Multilayer Carrier Accumulation Breaks the Limit Line of Silicon


 A novel Silicon Carbide gate-controlled bipolar field effect composite transistor with polysilicon region (SiC GCBTP) is proposed. Different from the traditional electrode connection mode of SiC VDMOS, the P+ region of P-well is connected with the gate in SiC GCBTP, and the polysilicon region is added between the P+ region and the gate. By this method, additional minority carriers can be injected into the drift region in on-state, and the distribution of minority carriers in the drift region will be optimized, so the on-state current is increased. In terms of static characteristics, it has the same high breakdown voltage (811V) as SiC VDMOS which length of drift is 5.5 μm. The on-state current of SiC GCBTP is 2.47×10-3 A/μm (V
 G=10V, V
 D=10V) which is 5.7 times that of SiC IGBT and 36.4 times that of SiC VDMOS. In terms of dynamic characteristics, the turn-on time of SiC GCBTP is only 0.425ns. And the turn-off time of SiC GCBTP is similar to SIC IGBT, which is 114.72ns.

SiC Gate-Controlled Bipolar Field Effect Composite Transistor with Polysilicon Region for Improving On-State Current

In this paper, a Multiplying Delay-Locked Loop (MDLL) for high-precision Time to Digital Converter(TDC) is proposed, which has low jitter and high delay linearity. In order to reduce the phase noise, an internally compensated charge pump(CP) is used to achieve better current matching between charging and discharging. The improved reverse differential delay cell structure is used to improve the resolution of multi-phase clock. An MDLL with an output frequency of 80-240MHz and an area of 0.08mm2 is realized by using 0.18um CMOS process. The test results show that the total power consumption under 1.8V power supply is 11.52mW@240MHz, RMS jitter is 10ps@240MHz.

A Multiplying Delay-Locked Loop design with low jitter and high linearity

In order to reduce the specific ON resistance (<inline-formula> <tex-math notation="LaTeX">$\text{R}_{\mathbf {{ \mathrm{\scriptscriptstyle ON}},sp}}$ </tex-math></inline-formula>) of power device in the drift region, the folded accumulation lateral double-diffused MOSFET (FALDMOS) is manufactured and analyzed in this article. The drift region of the FALDMOS is etched to form the folded surface, which is similar to the FinFET structure. The oxide inside the trench optimizes the electric field in the drift region, so the doping concentration can be increased while maintaining the breakdown voltage (BV). In addition, the trench increases the area of the drift region covered by the extended gate electrode, which can introduce more accumulated electrons when the device is turned on. The increased doping concentration and accumulated electrons work together to substantially increase the conductivity of the drift region, thereby obtaining ultralow <inline-formula> <tex-math notation="LaTeX">$\text{R}_{ \mathrm{\scriptscriptstyle ON},sp}$ </tex-math></inline-formula>. Furthermore, the folded accumulation LDMOS with split gate (FSLDMOS) is proposed to solve the phenomenon that the BV of the FALDMOS cannot be improved by increasing the drift length with the fixed oxide thickness. The polysilicon above the drift region is etched apart to form an extended gate and a split electrode. The electric field concentration near the drain can be alleviated by adjusting the bias on the split electrode. The FALDMOS and FSLDMOS are manufactured by the 0.35-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> BCD technology and the key processes, such as trench etching and polysilicon filling, are shown. The experimental results show that <inline-formula> <tex-math notation="LaTeX">$\text{R}_{ \mathrm{\scriptscriptstyle ON},sp}$ </tex-math></inline-formula> of the FALDMOS is only 9.3 <inline-formula> <tex-math notation="LaTeX">$\text{m}\Omega \cdot $ </tex-math></inline-formula>mm2, while that the conventional LDMOS is 36.2 <inline-formula> <tex-math notation="LaTeX">$\text{m}\Omega \cdot $ </tex-math></inline-formula>mm2, which is reduced by 74.3% with the same BV of 36 V. Moreover, the current density of FALDMOS is five times higher than that of the conventional LDMOS in the same areas. The BV of the FSLDMOS is improved by 66% compared with FALDMOS.

Accumulation-Mode Device: Experimental of LDMOS With Folded Drift Region Achieving Ultralow Specific ON Resistance

In this article, a novel vertical trench gate AlGaN/GaN metal–insulator–semiconductor field-effect transistor (MISFET) with semi-insulating polycrystalline silicon (SIPOS) field plates [SIPOS vertical trench gate AlGaN/GaN (VT-AlGaN/GaN) MISFET] is proposed for the first time. In the OFF-state, the electric field distribution in the n-GaN buffer is more uniform due to the presence of SIPOS field plates and deep trench structure, and the breakdown voltage (BV) is increased. Simulation results using Technology Computer-Aided Design (TCAD) Sentaurus show that under the same n-GaN buffer layer thickness (<inline-formula> <tex-math notation="LaTeX">$7~\mu \text{m}$ </tex-math></inline-formula>), the BVs of SIPOS VT-AlGaN/GaN MISFET and conventional vertical trench gate AlGaN/GaN MOSFET (conv.VT-AlGaN/GaN MOSFET) are 1828 and 1506 V, which increased 17.6%. In the ON-state, a majority carrier accumulation layer is formed on the surface between the n-GaN buffer and the thin Al2O3 layer. This high concentration electron region is equivalent to local high concentration doping region, and the specific ON-resistance (<inline-formula> <tex-math notation="LaTeX">${R}_{ \rm{ON,sp}}$ </tex-math></inline-formula>) of the device is greatly reduced. When the BV remains almost the same (1500 V), <inline-formula> <tex-math notation="LaTeX">${R}_{ \rm{ON,sp}}$ </tex-math></inline-formula> of SIPOS VT-AlGaN/GaN MISFET and conv.VT-AlGaN/GaN MOSFET is 0.63 and 1.03 <inline-formula> <tex-math notation="LaTeX">$\text{m}\Omega \cdot \text {cm}^{{2}}$ </tex-math></inline-formula>, respectively. <inline-formula> <tex-math notation="LaTeX">${R}_{ \rm{ON,sp}}$ </tex-math></inline-formula> decreased by 38.8%. The maximum figures of merit (FOMs) of the SIPOS-vertical AlGaN/GaN MISFET and conv.VT-AlGaN/ GaN MOSFET are 3.6 and 2.4 GW/cm2, respectively. The proposed SIPOS VT-AlGaN/GaN MISFET achieves a better compromise between BV and <inline-formula> <tex-math notation="LaTeX">${R}_{ \rm{ON,sp}}$ </tex-math></inline-formula>.

Simulation of AlGaN/GaN MISFET With 3.6-GW/cm2 High FOM by SIPOS Field Plates Electric Field Modulation

With the extensive application of stretchable flexible electronic circuits to wearable equipment and biomedicine, research on the electrical properties of such circuits has become a hot topic. In this paper, a flexible electronic design platform is established for the first time, realizing co-simulation of the mechanical and electronic aspects. The main functions of this platform include the design of stretchable interconnects, flexible devices, stretchable flexible electronic circuits, and stretchable flexible circuit-layout wiring. The following conclusions can be obtained: (1) With increased applied strain, the inductance of a stretchable interconnect will increase, while the delay and crosstalk will become non-negligible. (2) Although the performance of flexible passive devices does not change after transfer printing, the gate capacitor of the flexible MOS at the cut-off area does decrease. (3) Taking a flexible comparator as an example, the function and electrical performance of a flexible circuit are verified. (4) Taking a flexible amplifier circuit as an example, the flexible interconnection layout and wiring are simulated and verified.

Baoxing Duan

Papers

SiC Gate-Controlled Bipolar Field Effect Composite Transistor with Polysilicon Region for Improving On-State Current

A Multiplying Delay-Locked Loop design with low jitter and high linearity

Accumulation-Mode Device: Experimental of LDMOS With Folded Drift Region Achieving Ultralow Specific ON Resistance

Simulation of AlGaN/GaN MISFET With 3.6-GW/cm2 High FOM by SIPOS Field Plates Electric Field Modulation

A stretchable flexible electronic platform for mechanical and electrical collaborative design