Recent Advances in GaN‐Based Power HEMT Devices

A new superjunction LDMOS (SJ-LDMOS) is proposed with the step doping buffered layer under the SJ layer to obtain the low loss for the high-voltage region. The substrate-assisted depletion effect, which results from the p-type substrate for the n-channel SJ-LDMOS, has been eliminated by the step doping buffer layer. By the effect of the electric field modulation, a more uniform lateral electric filed is obtained due to the new high-electric field peaks introduced by the buffered step doping, which improves the breakdown voltage (BV) and average lateral electric field. Using ISE simulation, the BV of proposed SJ-LDMOST is increased by $\sim 50$ % than that of the conventional LDMOS, and improved by $\sim 32$ % than that of buffered SJ-LDMOS. The lateral average electric field is increased to 19 V/ $\mu $ m in the high-voltage region The experimental ${R} _{\mathbf {\mathrm{{\scriptstyle ON}},{\textrm sp}}}$ of the proposed SJ-LDMOS is 241 m $\Omega \,\cdot $ $\mathrm{cm}^{\mathrm {\mathbf {2}}}$ with a BV of 368 V, breaking the silicon limit relationship for ${R} _{\mathrm{{\scriptstyle ON}},\textrm {sp}}$ of 71.8 m $\Omega ~\cdot ~\mathrm{cm}^{\mathrm {\mathbf {2}}}$ with the BV of 242 V in the conventional LDMOS with the same drift region length The merit of BV/ $R _{\mathrm{{\scriptstyle ON}},\textrm {sp}}$ is 15.3 for the proposed SJ-LDMOS compared with that of 3.4 for the conventional LDMOS.

New Superjunction LDMOS Breaking Silicon Limit by Electric Field Modulation of Buffered Step Doping

A new lateral power MOSFET structure [folded-accumulation LDMOS (FALDMOS)] is proposed, in which the silicon-substrate surface is trenched to form a folded shape from the channel to the drain electrode and the gate is extended to the drain. The majority-carrier accumulation layer is formed as the device is in on state due to the extended gate in the drift region whose concentration is higher than that in a conventional LDMOS at the same breakdown voltage (BV), resulting from the additional electric-field modulation, and an extra majority carrier is introduced on the sidewall of the trench, which reduced the on-resistance of the drift region further. In addition, the channel density is doubled because of trenching the folded channel, which reduced the channel on-resistance. It indicates by simulation that the specific on-resistance of 4.6 mOmegamiddotmm2 with a BV of 27.4 V in FALDMOS is lower than that of the previously reported lowest one.

Folded-Accumulation LDMOST: New Power MOS Transistor With Very Low Specific On-Resistance

A new solution based on the concept of a deep drain diffusion combined with field plates (FPs) is proposed for the superjunction lateral double diffused MOSFET (SJ-LDMOS) device. The deep drain diffusion suppresses the curvature effect of the conventional SJ-LDMOS and the FPs optimize the electric field distribution further. Simulated results show that the proposed SJ-LDMOS exhibits figure of merits of 12.8 and 8.5 MW/cm $^{\mathrm{{2}}}$ for 700 and 1200 V ratings, respectively, which are about 20% better than the prior art. Moreover, the proposed SJ-LDMOS is less sensitive to the charge imbalance. Using the isotropic etch technique followed by implantation, the deep drain diffusion is easy to be fabricated.

A New Solution for Superjunction Lateral Double Diffused MOSFET by Using Deep Drain Diffusion and Field Plates

In this paper, a new power metal-oxide-semiconductor field-effect transistor (MOSFET) with a FS surface to reduce the specific on-resistance Ron,sp is proposed. Semi-insulating polycrystalline silicon (SIPOS) is deposited over a thin oxide layer. Drift-region concentration is higher in the proposed device than that of conventional lateral double-diffused MOS (LDMOS), and its structure with SIPOS is compared at the same breakdown voltage Bv. In the proposed MOSFET, the effect of electric-field modulation is improved, when compared with an accumulation LDMOS transistor (ALDMOST) due to a complete 3-D reduced surface-field effect. An extra multilayer majority carrier is introduced on the sidewalls of the trench, which reduces Ron,sp of the drift region. This indicates that the ideal silicon limit of the tradeoff of Bv and Ron,sp has been broken due to the lowest Ron,sp value in the proposed MOSFET. In the proposed MOSFET, Ron,sp (i.e., 13.5 mΩ·cm2) and Bv (i.e., 440 V) are improved greatly, when compared with the ALDMOST (i.e., with an Ron,sp of 26 mΩ·cm2 and Bv of 400 V) and a superjunction structure (i.e., with an Ron,sp of 98 mΩ·cm2 and Bv of 410 V).

Low Specific on-Resistance Power MOS Transistor With Multilayer Carrier Accumulation Breaks the Limit Line of Silicon

A new superjunction (SJ) LDMOS has been proposed with the complete charge compensation by the electric field modulation in this letter for the first time. The substrate-assisted depletion, produced due to the p-type substrate for the n-channel SJ-LDMOS, has been eliminated by the electric field modulation produced due to the step n-type buffered layer. The charge for the n- and p-type drifts has been depleted completely. Moreover, a new electric field peak has been introduced in the surface electric field distribution, which makes the lateral surface electric field uniform. The breakdown voltage has been improved for the new SJ-LDMOS compared with the conventional SJ-LDMOS because of the uniform surface electric field. By simulating and experimental results, the breakdown voltage of the new SJ-LDMOS with the electric field modulation has been increased by ~49% compared with the conventional LDMOS, and improved by ~30% compared with the conventional SJ-LDMOS.

New Superjunction LDMOS With the Complete Charge Compensation by the Electric Field Modulation

A novel lateral double-diffused MOSFET with multi-ring substrate (M-R LDMOS) is proposed. New high electric field peaks are introduced by the M-R due to the effect of the electric field modulation, which makes the lateral and vertical electric field distributions more uniform at the same time. As a consequence, the breakdown voltage (BV) of M-R LDMOS is enhanced significantly. The simulation result shows that the BV of M-R LDMOS is 566 V with the drift region length of $30~\mu \text{m}$ . Furthermore, the figure-of-merit of M-R LDMOS is 3.05 MW/cm2, increased by 190%, 45%, and 24.5% in comparison with the conventional LDMOS, the step doping drift LDMOS, and the assisted deplete-substrate layer LDMOS, respectively. M-R LDMOS has a much better performance. In addition, the proposed M-R LDMOS uses the highly doped substrate ( $3\times 10^{15}$ cm−3), which significantly reduces the cost of substrate.

Novel LDMOS Optimizing Lateral and Vertical Electric Field to Improve Breakdown Voltage by Multi-Ring Technology

A novel superjunction (SJ) lateral double-diffused MOSFET (LDMOS) with a deep High- K (HK) dielectric trench (HK SJ-LDMOS) is proposed and its mechanism is investigated by Technology Computer Aided Design (TCAD) simulations. The HK dielectric trench is embedded under the n+ drain, which is connected with the drain electrode. In the OFF-state, the reshaping effect of HK trench enhances the bulk electric field strength and weakens the peak electric field around the edge of the drain diffusion, which increases the breakdown voltage (BV). Moreover, because of the assistant depletion effect by the HK trench, a lower resistivity substrate is allowed for HK SJ-LDMOS, which also increases the doping concentration of the n-type buffer layer under the SJ layer of HK SJ-LDMOS, correspondingly. Thus, a lower specific ON-resistance ( ${R}_{ \mathrm{ ON},\text {sp}}$ ) is also obtained. Simulation results show that the BV increases by 35.2% in comparison with the conventional buffered SJ-LDMOS with the same drift length. Moreover, HK SJ-LDMOS presents an excellent figure of merit, which is two times higher than that of the conventional buffered SJ-LDMOS.

Novel Superjunction LDMOS With a High- K Dielectric Trench by TCAD Simulation Study

A novel concept of REBULF (REduced BULk Field) is proposed for the developing smart power integrated circuit with the thin epitaxy layer. The REBULF LDMOS structure is designed with N+ buried layer embedded in the high-resistance substrate. The mechanism of breakdown of the new device is that the high electric field around the drain is reduced by N+ buried layer, which causes the redistribution of the bulk electric field in the drift region of the REBULF LDMOS so that the substrate supports more biases. The critical condition of the REBULF technology is analyzed and validated by 2-D MEDICI simulation results, which is the product of the location of N+ buried layer and substrate’s doping is not more than 1 × 1012 cm−2. The breakdown voltage of REBULF LDMOS is increased by 75% in comparison to the conventional RESURF LDMOS from the simulation results. The experimental results show the high electric field around the drain is reduced as the depletion region spreads to N+ buried layer. Although the leakage has increased a little, this increase is not enough to cause the avalanche breakdown.

High voltage REBULF LDMOS with N+ buried layer

A new theory of lateral double-diffused MOS (LDMOS) by the folded-silicon substrate field-effect (FSLDMOS) with the complete 3-D REduced SURface Field (RESURF) is proposed in this paper for the first time The analytical model for the relationship between the breakdown voltage (BV) and the specific ON-resistance ( $R_{\rm \mathrm{\scriptscriptstyle ON},sp}$ ) of FSLDMOS is obtained, which breaks the limit relationship of the superjunction (SJ) LDMOS by applying three kinds of methods, including the additional electric-field modulation effect, majority carrier accumulation, and increasing the effective conduction paths simultaneously In the analytical model, the influence of the structural parameters of the folded-drift and electric field modulation coefficients is considered Besides, the optimal doping concentration of the folded-drift region for FSLDMOS is derived, which can give guidance for the dose of the folded-drift region The results indicate that a new analytical expression for the relationship between the BV and $R_{\mathrm{\scriptscriptstyle ON},\text {sp}}$ is obtained, which breaks the limit relationship of the SJ LDMOS by the complete 3-D RESURF All analytical results are well verified by the simulation results conducted by ISE-TCAD, showing the validity of the presented model

Baoxing Duan

Papers

New Superjunction LDMOS With the Complete Charge Compensation by the Electric Field Modulation

Novel LDMOS Optimizing Lateral and Vertical Electric Field to Improve Breakdown Voltage by Multi-Ring Technology

Novel Superjunction LDMOS With a High- K Dielectric Trench by TCAD Simulation Study

High voltage REBULF LDMOS with N+ buried layer

Theoretical Analyses of Complete 3-D Reduced Surface Field LDMOS With Folded-Substrate Breaking Limit of Superjunction LDMOS