Recent Advances in GaN‐Based Power HEMT Devices

A new superjunction LDMOS (SJ-LDMOS) is proposed with the step doping buffered layer under the SJ layer to obtain the low loss for the high-voltage region. The substrate-assisted depletion effect, which results from the p-type substrate for the n-channel SJ-LDMOS, has been eliminated by the step doping buffer layer. By the effect of the electric field modulation, a more uniform lateral electric filed is obtained due to the new high-electric field peaks introduced by the buffered step doping, which improves the breakdown voltage (BV) and average lateral electric field. Using ISE simulation, the BV of proposed SJ-LDMOST is increased by $\sim 50$ % than that of the conventional LDMOS, and improved by $\sim 32$ % than that of buffered SJ-LDMOS. The lateral average electric field is increased to 19 V/ $\mu $ m in the high-voltage region The experimental ${R} _{\mathbf {\mathrm{{\scriptstyle ON}},{\textrm sp}}}$ of the proposed SJ-LDMOS is 241 m $\Omega \,\cdot $ $\mathrm{cm}^{\mathrm {\mathbf {2}}}$ with a BV of 368 V, breaking the silicon limit relationship for ${R} _{\mathrm{{\scriptstyle ON}},\textrm {sp}}$ of 71.8 m $\Omega ~\cdot ~\mathrm{cm}^{\mathrm {\mathbf {2}}}$ with the BV of 242 V in the conventional LDMOS with the same drift region length The merit of BV/ $R _{\mathrm{{\scriptstyle ON}},\textrm {sp}}$ is 15.3 for the proposed SJ-LDMOS compared with that of 3.4 for the conventional LDMOS.

New Superjunction LDMOS Breaking Silicon Limit by Electric Field Modulation of Buffered Step Doping

A new lateral power MOSFET structure [folded-accumulation LDMOS (FALDMOS)] is proposed, in which the silicon-substrate surface is trenched to form a folded shape from the channel to the drain electrode and the gate is extended to the drain. The majority-carrier accumulation layer is formed as the device is in on state due to the extended gate in the drift region whose concentration is higher than that in a conventional LDMOS at the same breakdown voltage (BV), resulting from the additional electric-field modulation, and an extra majority carrier is introduced on the sidewall of the trench, which reduced the on-resistance of the drift region further. In addition, the channel density is doubled because of trenching the folded channel, which reduced the channel on-resistance. It indicates by simulation that the specific on-resistance of 4.6 mOmegamiddotmm2 with a BV of 27.4 V in FALDMOS is lower than that of the previously reported lowest one.

Folded-Accumulation LDMOST: New Power MOS Transistor With Very Low Specific On-Resistance

A new solution based on the concept of a deep drain diffusion combined with field plates (FPs) is proposed for the superjunction lateral double diffused MOSFET (SJ-LDMOS) device. The deep drain diffusion suppresses the curvature effect of the conventional SJ-LDMOS and the FPs optimize the electric field distribution further. Simulated results show that the proposed SJ-LDMOS exhibits figure of merits of 12.8 and 8.5 MW/cm $^{\mathrm{{2}}}$ for 700 and 1200 V ratings, respectively, which are about 20% better than the prior art. Moreover, the proposed SJ-LDMOS is less sensitive to the charge imbalance. Using the isotropic etch technique followed by implantation, the deep drain diffusion is easy to be fabricated.

A New Solution for Superjunction Lateral Double Diffused MOSFET by Using Deep Drain Diffusion and Field Plates

In this paper, a new power metal-oxide-semiconductor field-effect transistor (MOSFET) with a FS surface to reduce the specific on-resistance Ron,sp is proposed. Semi-insulating polycrystalline silicon (SIPOS) is deposited over a thin oxide layer. Drift-region concentration is higher in the proposed device than that of conventional lateral double-diffused MOS (LDMOS), and its structure with SIPOS is compared at the same breakdown voltage Bv. In the proposed MOSFET, the effect of electric-field modulation is improved, when compared with an accumulation LDMOS transistor (ALDMOST) due to a complete 3-D reduced surface-field effect. An extra multilayer majority carrier is introduced on the sidewalls of the trench, which reduces Ron,sp of the drift region. This indicates that the ideal silicon limit of the tradeoff of Bv and Ron,sp has been broken due to the lowest Ron,sp value in the proposed MOSFET. In the proposed MOSFET, Ron,sp (i.e., 13.5 mΩ·cm2) and Bv (i.e., 440 V) are improved greatly, when compared with the ALDMOST (i.e., with an Ron,sp of 26 mΩ·cm2 and Bv of 400 V) and a superjunction structure (i.e., with an Ron,sp of 98 mΩ·cm2 and Bv of 410 V).

Low Specific on-Resistance Power MOS Transistor With Multilayer Carrier Accumulation Breaks the Limit Line of Silicon

This paper reviews the physical breakdown mechanisms of Si-, SiC- and GaN-based power semiconductor devices. In the off-state in which Si-based Lateral Double-diffused MOS (LDMOS), SiC-base...

Breakdown Mechanisms of Power Semiconductor Devices

A depletion-mode AlGaN/GaN high electron mobility transistors (HEMTs) have been proposed in this article with the partial GaN cap, which applies the electric field modulation effect to optimize the surface electric field and two-dimensional electron gas (2DEG) distribution. The 2DEG density under the partial GaN cap is reduced due to the polarization effect formed by the partial GaN cap and AlGaN layers. The surface electric field is reshaped by the electric field modulation effect due to the partial GaN cap, featuring an extra electric field peak far away from the gate edge, which, therefore, improves the breakdown voltage (BV). Moreover, the output current ( ${I}_{\text {DS}}$ ) is also improved slightly resulting from the increased mobility of 2DEG, which compensates for the decrease in the 2DEG density. The experimental BV is increased greatly from 378 V for the conventional AlGaN/GaN HEMTs to 656 V for the depletion-mode partial cap layer AlGaN/GaN HEMTs because of the optimized surface electric field by the electric field modulation effect. The maximum output current ( ${I}_{\text {max}}$ ) is increased from 538 to 558 mA/mm. It is concluded that the BV can be improved significantly and ${I}_{\text {DS}}$ increased slightly for AlGaN/GaN HEMTs by the electric field modulation technique using the partial GaN cap, which optimizes the BV and specific ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}, \text {sp}}$ ) simultaneously.

Experimental Results for AlGaN/GaN HEMTs Improving Breakdown Voltage and Output Current by Electric Field Modulation

A new theory about terminal technology is proposed for superjunction lateral double-diffused metal–oxide–semiconductor field effect transistors with multiple floating buried layers (MFBL SJ-LDMOS) based on the bulk electric field (E-field) modulation in this paper for the first time. A concise and efficient analytical theory is presented to predict the vertical voltage and bulk E-field distributions of MFBL SJ-LDMOS. The analytical formulas for the breakdown voltage (BV) and the vertical peak E-field of MFBL SJ-LDMOS are derived in the closed-form equations, which starts from a single floating buried layer for the vertical E-field modulation, extending this theory to predict the vertical E-field peaks and vertical voltage distributions between the MFBLs. Quantitative analytical description has been given to explain the bulk E-field modulation for the MFBL. Moreover, the optimal spacing and the maximum BV are procedurally predicted. All analytical results are well verified by the 3-D numerical simulations, proving the applicability of the method presented in other power devices with MFBL including MFBL LDMOS, MFBL lateral insulated gate bipolar transistor, and MFBL diode.

Baoxing Duan

Papers

Breakdown Mechanisms of Power Semiconductor Devices

Experimental Results for AlGaN/GaN HEMTs Improving Breakdown Voltage and Output Current by Electric Field Modulation

Theory Analyses of SJ-LDMOS With Multiple Floating Buried Layers Based on Bulk Electric Field Modulation

Analytical Models for the electric field and potential of AlGaN/GaN HEMT with partial silicon doping

Breakdown point transfer theory for Si/SiC heterojunction LDMOS with deep drain region