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Beak-Hyung Cho
Researcher at Samsung
Publications - 92
Citations - 2207
Beak-Hyung Cho is an academic researcher from Samsung. The author has contributed to research in topics: Semiconductor memory & Memory cell. The author has an hindex of 26, co-authored 92 publications receiving 2194 citations.
Papers
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Journal ArticleDOI
A 90 nm 1.8 V 512 Mb Diode-Switch PRAM With 266 MB/s Read Throughput
Kwang-Jin Lee,Beak-Hyung Cho,Woo-Yeong Cho,Sang-beom Kang,Byung-Gil Choi,Hyung-Rok Oh,Chang-Soo Lee,Hye-Jin Kim,Joon-Min Park,Qi Wang,Mu-Hui Park,Yu-Hwan Ro,Joon-Yong Choi,Ki-Sung Kim,Young-Ran Kim,In-Cheol Shin,Ki-won Lim,Ho-Keun Cho,Chang-han Choi,Won-Ryul Chung,Du-Eung Kim,Yong-Jin Yoon,Kwang-Suk Yu,Gitae Jeong,Hongsik Jeong,Choong-keun Kwak,Chang-Hyun Kim,Kinam Kim +27 more
TL;DR: A 512 Mb diode-switch PRAM developed in a 90 nm CMOS technology using the SEG technology has achieved minimum cell size and disturbance-free core operation and achieved read throughput of 266 MB/s through the proposed schemes.
Proceedings ArticleDOI
A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput
Kwang-Jin Lee,Beak-Hyung Cho,Woo-Yeong Cho,Sang-beom Kang,Byung-Gil Choi,Hyung-Rok Oh,Chang-Soo Lee,Hye-Jin Kim,Joon-Min Park,Qi Wang,Mu-Hui Park,Yu-Hwan Ro,Joon-Yong Choi,Ki-Sung Kim,Young-Ran Kim,In-Cheol Shin,Ki-won Lim,Ho-Keun Cho,Chang-han Choi,Won-Ryul Chung,Du-Eung Kim,Kwang-Suk Yu,Gitae Jeong,Hongsik Jeong,Choong-keun Kwak,Chang-Hyun Kim,Kinam Kim +26 more
TL;DR: A core configuration, read/write circuit techniques, and a charge-pump system for the diode-switch PRAM are described, which achieves read throughput of 266MB/S and maximum write throughput of 4.64 MB/S with a 1.8V supply.
Journal ArticleDOI
A 0.1- $\mu{\hbox {m}}$ 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation
Sang-beom Kang,Woo Yeong Cho,Beak-Hyung Cho,Kwang-Jin Lee,Chang-Soo Lee,Hyung-Rok Oh,Byung-Gil Choi,Qi Wang,Hye-Jin Kim,Mu-Hui Park,Yu Hwan Ro,Su-Yeon Kim,Choong-Duk Ha,Ki-Sung Kim,Young-Ran Kim,Du-Eung Kim,Choong-keun Kwak,Hyun-Geun Byun,Gitae Jeong,Hongsik Jeong,Kinam Kim,Yun-Seung Shin +21 more
TL;DR: A 256-Mb phase-change random access memory has been developed, featuring 66-MHz synchronous burst-read operation, featuring endurance and retention characteristics measured to be 107 cycles and ten years at 99 degC.
Patent
Semiconductor memory device with stacked memory cell and method of manufacturing the stacked memory cell
TL;DR: In this article, a hierarchical bit line structure was proposed to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the resistive-change memory cells.
Journal ArticleDOI
Enhanced write performance of a 64 Mb phase-change random access memory
Hyung-Rok Oh,Beak-Hyung Cho,Woo Yeong Cho,Sang-beom Kang,Byung-Gil Choi,Hye-Jin Kim,Ki-Sung Kim,Du-Eung Kim,Choong-keun Kwak,Hyun-Geun Byun,Gitae Jeong,Hongsik Jeong,Kinam Kim +12 more
TL;DR: A 1.8 V 64 Mb phase-change RAM with improved write performance is fabricated in a 0.12 /spl mu/m CMOS technology for RESET and SET distributions based on cell current regulation and multiple step-down pulse generators.