Du-Eung Kim

TL;DR: A 512 Mb diode-switch PRAM developed in a 90 nm CMOS technology using the SEG technology has achieved minimum cell size and disturbance-free core operation and achieved read throughput of 266 MB/s through the proposed schemes.

TL;DR: A core configuration, read/write circuit techniques, and a charge-pump system for the diode-switch PRAM are described, which achieves read throughput of 266MB/S and maximum write throughput of 4.64 MB/S with a 1.8V supply.

TL;DR: A 256-Mb phase-change random access memory has been developed, featuring 66-MHz synchronous burst-read operation, featuring endurance and retention characteristics measured to be 107 cycles and ten years at 99 degC.

TL;DR: In this article, a hierarchical bit line structure was proposed to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the resistive-change memory cells.

TL;DR: A 1.8 V 64 Mb phase-change RAM with improved write performance is fabricated in a 0.12 /spl mu/m CMOS technology for RESET and SET distributions based on cell current regulation and multiple step-down pulse generators.