Showing papers by "Bernd Tillack published in 2003"

SiGe:C BiCMOS technology with 3.6 ps gate delay

Abstract: A high-speed SiGe:C HBT technology is presented that combines a new extrinsic base construction with a low-resistance collector design to simultaneously minimize base and collector resistances and base-collector capacitance A ring oscillator delay of 36 ps per stage was achieved To our knowledge, this is the shortest gate delay reported to date for a SiGe technology The HBTs demonstrate an f/sub T/ of 190 GHz, an f/sub max/ of 243 GHz, and a BV/sub CEO/ of 19 V at an drawn emitter size of 0175/spl times/084 /spl mu/m/sup 2/ The high-speed HBT module has been integrated in a 025 /spl mu/m CMOS platform

Atomically Controlled Technology for Future Si-Based Devices

Abstract: One of the main requirements for Si-based Ultrasmall device is atomic-order control of process technology. Here we show the concept of atomic-l evel processing based on atomic-order surface reaction control. The main idea of the atomi c layer approach is the separation of the surface adsorption of reactant gases from the re action process. Self-limiting formation of 1-3 atomic layers of group IV or related atoms in the thermal adsorption and reaction of hydride gases (SiH 4, GeH4, NH3, PH3, CH4 and SiH3CH3) on Si(100) and Ge(100) are generalized based on the Langmuir-type model. Si or SiGe epitaxial growth over the N, P and B layer already-formed on Si(100) or SiGe(100) surface is achi eved. It is found that higher level of electrical P atoms exist in such film, compar ed with doping under thermal equilibrium conditions. Furthermore, the capability of atomically contr olled processing for doping of advanced devices with critical requirements for dose and loc ation control is demonstrated for the base doping of SiGe:C heterojunction bipolar trans is ors (HBTs). These results open the way to atomically controlled technology for ultra-large-sca l integrations.

Impact of Defects on the Leakage Currents of Si/SiGe/Si Heterojunction Bipolar Transistors

Abstract: We investigate the impact of defects on the leakage currents of Si/SiGe/Si heterojunction bipolar transistors (HBTs). We demonstrate that threading dislocations in the HBT layer stack strongly increase the leakage currents. Such defects can be formed during an a neal step for the high-dose implantation commonly used to prepare a low-ohmic subcollector. Defect bands and threading dislocations were observed in case of P implantation while Sb implant ation leads to defect-free layers and devices with a low leakage current level. We also show that defects arising during the deposition process of the epitaxial Si/SiGe/Si layer stack have a strong impact on the leakage currents of HBTs. Darkfield microscopy was applied to evaluate the surface defect density of deposited Si/SiGe/Si layer stacks. We demonstrate that this me thod is very sensitive and capable for a defect-related layer classification, and that there is a c orrelation between the different defect classes and the leakage currents. Introduction The radio frequency (RF) performance of Si/SiGe/Si-npn HBTs has be en tr mendously improved over the last 10 years [1,2]. Si/SiGe/Si HBTs are no longer niche devices, in particular when embedded in a BiCMOS technology which strongly increases the require ments of HBT yield and reliability. The improvement of the HBT RF performance is a res ult of a strong reduction of the lateral and vertical device dimensions combined with increased doping l evels. Defect-free fabrication of highly doped BiCMOS HBTs is a challenge. It require s th analysis of the fabrication process with respect to defect sources and a careful choice of the process conditions for defectcritical steps, like implantations, anneals, or deposition of epitaxia l layers. Moreover, suitable methods for defect detection and characterization are needed and the s pecific impact of different defects on the junction leakage currents has to be found out. In this paper we focus on implantation defects induced by high-dose implant ation applied for the formation of highly doped HBT subcollectors. We will demonstrate that t reading dislocations formed during the anneal step following the implantation, strongly incre ase the HBT leakage currents. In case of P implantation, we observed defect bands originati n such threading dislocations while Sb implantation led to defect-free layers and de vices with a low leakage current level. In the second part of the paper we show that defects arising during t he deposition process for the epitaxial Si/SiGe/Si layer stack have a strong impact on the HBT leakage currents, too. We will demonstrate that darkfield microscopy is a suitable method for a def ect-r lated layer classification and that there is a correlation between the different defect classes and HBT le akage currents. Solid State Phenomena Online: 2003-09-30 ISSN: 1662-9779, Vols. 95-96, pp 249-254 doi:10.4028/www.scientific.net/SSP.95-96.249 © 2004 Trans Tech Publications Ltd, Switzerland All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications Ltd, www.scientific.net. (Semanticscholar.org-18/03/20,13:30:54) Experimental Fig.1a shows a schematic cross section of the HBT structure used for leakage cur rent measurements. This simple double mesa structure allows us to carry out electri cal measurements already after contact silicidation which strongly reduces preparation times. The e mitter dimensions of this structure are large (100x100 μm ) which excludes the influence of perimeter effects. We measure d the collector to emitter leakage current I CEO (grounded emitter, V CE = 1V) and the emitter to collector leakage current I ECO (grounded collector, V CE = -1V) in both cases with floating base. In the ICEO regime, both electrically active defects in the collector-bas e depletion region and collectoremitter shorts (pipes) can be detected while the I ECO regime delivers additional information about the impact of defects in the emitter-base depletion region. Fig.1. Schematic of a HBT (a) and a typical Si/SiGe/Si-HBT vertical str uctu e (b). Fig.1b shows the vertical structure of the HBT active region, includi ng the subcollector, the epitaxial Si/SiGe/Si layer stack, and a highly doped emitter l ayer. The epitaxial deposition is carried out after a wet chemical cleaning and a hydrogen prebake by means of chemical vapor deposition at low pressure and temperatures at 700°C for the silicon and 500°C for the SiGe deposition. Subcollector implantation induced defects Low-ohmic subcollector regions of npn bipolar transistors are commonly r ea ized by high-dose P, As, or Sb implantation. Depending on species and ion energy during implantation, amorphous layer s of different thickness and depth are generated. During the following anne al step the amorphous layer recrystallizes, in some cases leaving behind defect bands at the former interfaces between amorphous and crystalline regions. Fig.2 shows TEM cross sections of H BTs differing in the structure of the implanted subcollector. The device with the P subcolle ctor shows various types of defects, like a defect band with a high dislocation density located some hundr ed nanometers beneath the SiGe base layer, but also a single threading dislocation which rea es from this defect band to the SiGe layer (Fig.2a). In contrast, no defects could be detected by means of TEM for the HBT structure with Sb subcollector (Fig.2b). The improved defect behavior of t he Sb subcollector mainly results from the higher atomic mass and the lower implantation ene rgy. It results in a shallower amorphous region after implantation which expands up to the wafer surfac e en bling a defect-free recrystallization during the anneal step. (b) Base Emitter

Semiconductor component used as a MOSFET comprises an active semiconductor region and an insulating region which laterally delimits the active semiconductor region

Abstract: Semiconductor component comprises an active semiconductor region (11) and an insulating region (13) which laterally delimits the active semiconductor region. The insulating region is made from a material selected so that an uniaxial or biaxial lattice dilation with a predetermined value. An independent claim is also included for a process for the production of a semiconductor component.