P
Peter Schley
Researcher at Innovations for High Performance Microelectronics
Publications - 49
Citations - 1026
Peter Schley is an academic researcher from Innovations for High Performance Microelectronics. The author has contributed to research in topics: CMOS & Heterojunction bipolar transistor. The author has an hindex of 16, co-authored 49 publications receiving 996 citations.
Papers
More filters
Journal ArticleDOI
A 0.13 $\mu{\hbox {m}}$ SiGe BiCMOS Technology Featuring f $_{T} $ /f $_{\max}$ of 240/330 GHz and Gate Delays Below 3 ps
Holger Rucker,Bernd Heinemann,Wolfgang Winkler,R. Barth,J. Borngraber,Juergen Drews,G.G. Fischer,A. Fox,Thomas Grabolla,Ulrich Haak,Dieter Knoll,Falk Korndörfer,Andreas Mai,Steffen Marschmeyer,Peter Schley,Daniel Schmidt,J. Schmidt,Markus Andreas Schubert,K. Schulz,Bernd Tillack,Dirk Wolansky,Yuji Yamamoto +21 more
TL;DR: A 0.13 µm SiGe BiCMOS technology for millimeter wave applications is presented and ring oscillator gate delays of 2.9 ps, low-noise amplifiers for 122 GHz, and LC oscillators for frequencies above 200 GHz are demonstrated.
Proceedings ArticleDOI
Novel collector design for high-speed SiGe:C HBTs
Bernd Heinemann,Holger Rucker,R. Barth,J. Bauer,D. Bolze,E. Bugiel,J. Drews,K.E. Ehwald,Thomas Grabolla,U. Haak,W. Hoppner,D. Knoll,D. Krüger,B. Kuck,R. Kurps,M. Marschmeyer,H.H. Richter,Peter Schley,D. Schmidt,R. Scholz,Bernd Tillack,Wolfgang Winkler,D. Wolnsky,H.-E. Wulf,Yuji Yamamoto,Peter Zaumseil +25 more
TL;DR: In this paper, a collector design for high-frequency SiGe:C HBTs without deep trenches and with low-resistance collectors formed by high-dose ion implantation after shallow trench formation was described.
Proceedings ArticleDOI
A 0.13µm SiGe BiCMOS technology featuring f T /f max of 240/330 GHz and gate delays below 3 ps
Holger Rucker,Bernd Heinemann,Wolfgang Winkler,R. Barth,J. Borngraber,J. Drews,G. G. Fischer,A. Fox,Thomas Grabolla,U. Haak,D. Knoll,F. Korndorfer,Andreas Mai,Steffen Marschmeyer,Peter Schley,D. Schmidt,J. Schmidt,K. Schulz,Bernd Tillack,D. Wolansky,Yuji Yamamoto +20 more
TL;DR: In this paper, a 0.13 µm SiGe BiCMOS technology for millimeter wave applications is presented, which features high-speed HBTs (f T =240 GHz, f max =330 GHz, BV CEO =1.7 V) along with high-voltage high-frequency HBT (fT =50 GHz, F max =130 GHz, BS CEO =3.7V) integrated in a dual-gate, triple-well RF-CMOS process.
Proceedings ArticleDOI
SiGe:C BiCMOS technology with 3.6 ps gate delay
H. Rucker,Bernd Heinemann,R. Barth,D. Bolze,J. Drews,Ulrich Haak,W. Hoppner,D. Knoll,K. Kopke,Steffen Marschmeyer,Harald H. Richter,Peter Schley,D. Schmidt,R. Scholz,Bernd Tillack,Wolfgang Winkler,H.-E. Wulf,Yuji Yamamoto +17 more
TL;DR: In this article, a high-speed SiGe:C HBT is presented that combines a new extrinsic base construction with a low-resistance collector design to simultaneously minimize base and collector resistances and base collector capacitance.
Patent
Layers in substrate wafers
TL;DR: In this paper, the authors proposed to provide layers in substrate wafers with which the drawbacks of conventional assemblies are overcome in order to achieve an adequate resistance to latch-up in highly scaled, digital CMOS circuits with comparatively low costs and, on the other hand, to ensure low substrate losses/couplings for analog high-frequency circuits and, in addition, to influence the component behavior in a nondestructive manner.