Technical foundations introduction software reliability and system reliability the operational profile software reliability modelling survey model evaluation and recalibration techniques practices and experiences best current practice of SRE software reliability measurement experience measurement-based analysis of software reliability software fault and failure classification techniques trend analysis in validation and maintenance software reliability and field data analysis software reliability process assessment emerging techniques software reliability prediction metrics software reliability and testing fault-tolerant SRE software reliability using fault trees software reliability process simulation neural networks and software reliability. Appendices: software reliability tools software failure data set repository.

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Handbook of software reliability engineering

Design and Analysis ofFault-Tolerant Digital Systems: B. W. JOHNSON (Addison Wesley, 1989,577 pp., £41.35) The book provides an introduction to the important aspects of designing fault-tolerant systems, and an evaluation of how well the reliability goals have been achieved. The book is mainly oriented towards a final year undergraduate course on fault-tolerant computing, primarily with an implementation bias. In chapters 1 and 2, definitions and basic terminology are covered, which sets the stage for the remaining chapters, and provides the background and motivation for the remainder of the book. Chapter 3 provides a thorough analysis of fault-tolerance techniques and concepts. This chapter in particular is remarkably well written, covering the issues of hardware and information redundancy, which form the mainstay offault-tolerant computing. Subsequent chapters on the use and evaluation of the various approaches illustrate the principles as they have been put into practice. At the end of chapter 5, small projects that allow the reader to apply the material presented in the preceding chapters are included. The resurgence of interest in fault-tolerance with the emergence of VLSI is the theme of chapter 6, focussing on designing fault-tolerant systems in a VLSI environment. The problems and opportunities presented by VLSI are discussed and the use of redundancy techniques in order to enhance manufacturing yield and to provide in-service reliability are reviewed. The final chapter covers testing, design for testability and testability analysis, which must be considered during each phase of the design process to guarantee that resulting designs can be thoroughly tested. Each chapter is followed by a summary of the key issues and concepts presented therein, and a separate list of references, which makes it easily readable. In addition, there is a reading list with more comprehensive and specialised references devoted to each chapter. Overall, the book is well written, and contains a great deal of information in 577 pages. The book has a definite implementation bias, and draws considerably on the author's experience in industry, particularly reflected in the projects accompanying chapter 5. The book should be a useful addition to a library, and a suitable text to accompany a lecture course on fault-tolerant computing. R. RAMASWAMI, Department ofComputation, UMIST

Book Review: Design and Analysis of Fault-Tolerant Digital SystemsDesign and Analysis of Fault-Tolerant Digital Systems: JohnsonB. W. (Addison Wesley, 1989, 577 pp., £41.35)

http://www.lcc.uma.es/~eat/pdf/itor2013.pdf

Parallel metaheuristics: recent advances and new trends

High-performance CMOS variability in the 65-nm regime and beyond. IBM J Res And Dev

Systems, devices, methods, and kits for monitoring one or more physiologic and/or physical signals from a subject are disclosed. A system including patches and corresponding modules for wirelessly monitoring physiologic and/or physical signals is disclosed. A service system for managing the collection of physiologic data from a customer is disclosed. An isolating patch for providing a barrier between a handheld monitoring device with a plurality of contact pads and a subject is disclosed.

Modular physiologic monitoring systems, kits, and methods

In situ X-ray fluorescence used for real-time control of CuInxGa1−xSe2 thin film composition

This chapter provides an overview of fault-tolerant computing. Fault-tolerant computing can be defined as the process by which a computing system continues to perform its specified tasks correctly in the presence of faults with the goal of improving the dependability of the system. Principles of fault-tolerant computing as well as various fault-tolerant architectures are discussed. The article concludes by observing trends in the fault-tolerant computing.


Keywords:

fault tolerance;
reliability;
availability;
coverage;
dependability;
redundancy

Fault-Tolerant Computing

Microfluidics-based biochips consist of microfluidic arrays on rigid substrates through which movement of fluids is tightly controlled to facilitate biological reactions. Biochips are soon expected to revolutionize biosensing, clinical diagnostics, environmental monitoring, and drug discovery. Critical to the deployment of the biochips in such diverse areas is the dependability of these systems. Thus robust testing and diagnosis techniques are required to ensure adequate level of system dependability. Due to the underlying mixed technology and mixed energy domains, such biochips exhibit unique failure mechanisms and defects. In this article efficient parallel testing and diagnosis algorithms are presented that can detect and locate single as well as multiple faults in a microfluidic array without flooding the array, a problem that has hampered realistic implementation of several existing strategies. The fault diagnosis algorithms are well suited for built-in self-test that could drastically reduce the operating cost of microfluidic biochip. Also, the proposed alogirthms can be used both for testing and fault diagnosis during field operation as well as increasing yield during the manufacturing phase of the biochip. Furthermore, these algorithms can be applied to both online and offline testing and diagnosis. Analytical results suggest that these strategies that can be used to design highly dependable biochip systems.

Efficient parallel testing and diagnosis of digital microfluidic biochips

A wireless system for brain monitoring/mapping of neurological-disorder patients includes a plurality of electrodes each configured for surface abutment of brain tissue and main circuitry for placement outside a body of a patient and configured to transmit power at radio frequencies and send and receive data using infrared energy. Remote circuitry is provided for subcutaneous implantation in a head of the patient. The remote circuitry is connected to the plurality of electrodes and includes a multiplexer sampling signals from the plurality of electrodes. The multiplexer outputs electrode signals to an amplifier and A/D converter for transmission to the main circuitry. The remote circuitry is configured to (a) receive transmitted power at radio frequencies from the main circuitry, (b) capture and digitize full-bandwidth EEG signals from each of the electrodes, and (c) send data to and receive data from the main circuitry using infrared energy.

Wireless system for epilepsy monitoring and measurement

The new generation of shared memory multi-core processors with multiple parallel execution paths provides a promising hardware platform for applications with high degree of task-level parallelism (TLP). Genetic Algorithm (GA), a widely-used evolutionary meta-heuristic optimization method, is a unique candidate in this class of applications and demonstrates significant amount of explicit and implicit parallelism. In this paper, we present the performance characteristics of a GA optimizing a placement problem on a Sun UltraSPARC T1 processor. To investigate the behavior of the benchmark, we vary both algorithm-specific parameters as well as the size of the target problem. The system performance is evaluated by monitoring throughput, cycle-per-instruction (CPI) and, the memory access patterns for different core and thread combinations. Our experiments show that for a constant data size, as the number of threads per core increase from 1 to 4, the throughput of the system increases by 84% keeping all cores active. Similarly, as we increase the number of cores in the system, the throughput of the system increases by a factor of 3. The average memory bandwidth is seen to scale in proportion to throughput for both core-scaling and thread-scaling. The overall increase in throughput, either by core-scaling or thread-scaling, in spite of growing memory bandwidth, shows the ability of the multi-threaded multi-core processor to hide long latency memory accesses for the targeted benchmark.

Bharat Joshi

Papers

In situ X-ray fluorescence used for real-time control of CuInxGa1−xSe2 thin film composition

Fault-Tolerant Computing

Efficient parallel testing and diagnosis of digital microfluidic biochips

Wireless system for epilepsy monitoring and measurement

Performance analysis of coarse-grained parallel genetic algorithms on the multi-core sun UltraSPARC T1