An interference modulator (Imod) incorporates anti-reflection coatings and/or micro-fabricated supplemental lighting sources. An efficient drive scheme is provided for matrix addressed arrays of IMods or other micromechanical devices. An improved color scheme provides greater flexibility. Electronic hardware can be field reconfigured to accommodate different display formats and/or application functions. An IMod's electromechanical behavior can be decoupled from its optical behavior. An improved actuation means is provided, some one of which may be hidden from view. An IMod or IMod array is fabricated and used in conjunction with a MEMS switch or switch array. An IMod can be used for optical switching and modulation. Some IMods incorporate 2-D and 3-D photonic structures. A variety of applications for the modulation of light are discussed. A MEMS manufacturing and packaging approach is provided based on a continuous web fed process. IMods can be used as test structures for the evaluation of residual stress in deposited materials.

Photonic mems and structures

We develop detailed area and energy models for on-chip interconnection networks and describe tradeoffs in the design of efficient networks for tiled chip multiprocessors. Using these detailed models we investigate how aspects of the network architecture including topology, channel width, routing strategy, and buffer size affect performance and impact area and energy efficiency. We simulate the performance of a variety of on-chip networks designed for tiled chip multiprocessors implemented in an advanced VLSI process and compare area and energy efficiencies estimated from our models. We demonstrate that the introduction of a second parallel network can increase performance while improving efficiency, and evaluate different strategies for distributing traffic over the subnetworks. Drawing on insights from our analysis, we present a concentrated mesh topology with replicated subnetworks and express channels which provides a 24% improvement in area efficiency and a 48% improvement in energy efficiency over other networks evaluated in this study.

http://cva.stanford.edu/publications/2006/jbalfour_ICS.pdf

Design tradeoffs for tiled CMP on-chip networks

One aspect of the invention provides a method for fabricating a microelectromechanical systems device. The method comprises fabricating an array of first elements, each first element conforming to a first geometry; fabricating at least one array of second elements, each second element conforming to a second geometry; wherein fabricating the arrays comprises selecting a defining aspect of each of the first and second geometries based on a defining characteristic of each of the first and second elements; and normalizing differences in an actuation voltage required to actuate each of the first and second elements, wherein the differences are as a result of the selected defining aspect, the defining characteristic of each of the elements being unchanged.

A microelectromechanical systems device and method for fabricating same

The invention provides a microfabrication process which may be used to manufacture a MEMS device. The process comprises depositing one or a stack of layers on a base layer, said one layer or an uppermost layer in said stack of layers being a sacrificial layer; patterning said one or a stack of layers to provide at least one aperture therethrough through which said base layer is exposed; depositing a photosensitive layer over said one or a stack of layers; and passing light through said at least one aperture to expose said photosensitive layer.

A method for fabricating a structure for a microelectromechanical systems (mems) device

An interferometric modulator manufactured according to a particular set of processing parameters may have a non-zero offset voltage. A process has been developed for modifying the processing parameters to shift the non-zero offset voltage closer to zero. For example, the process may involve identifying a set of processing parameters for manufacturing an interferometric modulator that results in a non-zero offset voltage for the interferometric modulator. The set of processing parameters may then be modified to shift the non-zero offset voltage closer to zero. For example, modifying the set of processing parameters may involve modifying one or more deposition parameters used to make the interferometric modulator, applying a current (e.g., a counteracting current) to the interferometric modulator, and/or annealing the interferometric modulator. Interferometric modulators made according to the set of modified processing parameters may have improved performance and/or simpler drive schemes.

Process for modifying offset voltage characteristics of an interferometric modulator

A Micro Electro-Mechanical System (MEMS) switch (100) having a bottom electrode (116) formed over a substrate (112) and a thin protective cap layer (130) disposed over the bottom electrode (116). A dielectric material (118) is disposed over the protective cap layer (130) and a pull-down electrode (122) is formed over the spacer (120) and the dielectric material (118). The protective cap layer (130) prevents the oxidation of the bottom electrode (116). The thin protective cap layer (130) comprises a metal having an associated oxide with a high dielectric constant. A portion (132) of the thin protective cap layer (130) may oxidize during the formation of the dielectric material (118), increasing the capacitance of the dielectric stack (128).

Microelectromechanical switch with fixed metal electrode/dielectric interface with a protective cap layer

A Micro Electro-Mechanical System (MEMS) varactor (100, 200) having a bottom electrode (116) formed over a substrate (112) and a dielectric material (130) disposed over the bottom electrode (116) A pull-down electrode (122) is formed over spacer (120) and the dielectric material (130) The MEMS varactor (100, 200) is adapted to operate in a stiction mode, with at least a portion of pull-down electrode (122) in contact with dielectric material (130) The MEMS varactor (100, 200) has a high Q, large tuning range, and high sensitivity

High Q-large tuning range micro-electro mechanical system (MEMS) varactor for broadband applications

The use of a high-resistivity substrate extends the capability of standard digital CMOS technology to enable the integration of high-performance RF passive components. The impact of substrate resistivity on the key components of RF CMOS for system-on-chip (SoC) applications is discussed. The comparison includes the transistor, transmission line, inductor, capacitor and varactor, as well as the noise isolation. We also discuss the integration issues including latch-up and well-well isolation in a 0.35-/spl mu/m Cu metal pitch, 0.1-/spl mu/m-gate-length RF CMOS technology.

RF CMOS on high-resistivity substrates for system-on-chip applications

The present invention provides an apparatus and method of selecting a unique combination of materials and dimensions for fabrication of a micro-electromechanical switch for improved RF switch performance. An electrode material is selected which exhibits a resistivity resulting in improved insertion loss for a predetermined switching speed, a dielectric material is selected which exhibits a permittivity resulting in improved isolation, and an airgap thickness is selected resulting in a pull-down voltage approximately equal to a supply voltage of the micro-electromechanical switch in which the isolation and predetermined switching speed are also functions of the airgap thickness.

Selection of materials and dimensions for a micro-electromechanical switch for use in the RF regime

An inductor structure (102) formed in an integrated circuit (100) is disclosed, and includes a first isolation layer (106) and a first core plate (104) disposed over or within the first isolation layer (106, 114). The first core plate (104) includes a plurality of electrically coupled conductive traces composed of a conductive ferromagnetic material layer. A second isolation layer (108) overlies the first isolation layer and an inductor coil (102) composed of a conductive material layer (118) is formed within the second isolation layer (108). Another core plate may be formed over the coil. The one or more core plates increase an inductance (L) of the inductor coil (102).

Byron Lovell Williams

Papers

Microelectromechanical switch with fixed metal electrode/dielectric interface with a protective cap layer

High Q-large tuning range micro-electro mechanical system (MEMS) varactor for broadband applications

RF CMOS on high-resistivity substrates for system-on-chip applications

Selection of materials and dimensions for a micro-electromechanical switch for use in the RF regime

Method to improve inductance with a high-permeability slotted plate core in an integrated circuit