Applied and numerical harmonic analysis

A Software-Defined GPS and Galileo Receiver

This paper presents an overview of technical challenges in achieving higher integration levels, lower power dissipation, smaller form factor, and lower cost in portable battery-powered RF transceivers for personal communications applications. Specific emphasis is placed on silicon integrated circuits for transceivers in the 800 MHz-2.5 GHz range of frequencies.

Future directions in silicon ICs for RF personal communications

The contributions of integrated circuits to the RF front-end of wireless receivers and transmitters operating in broadcast and personal communications bands are surveyed. It is seen from this that when ICs enable a rethinking of the RF architecture, the wireless device can sometimes become significantly smaller, and consume much less power. Examples are taken from FM broadcast receivers, pagers, and cellular telephone handsets. Many semiconductor technologies are competing today to supply RF-ICs to cellular telephones. The various design styles and levels of integration are compared, with the conclusion that single-chip silicon transceivers, combined with architectures which substantially reduce off-chip passive components, will likely dominate digital cellular telephones in the near future. The survey also projects future trends for ICs for miniature spread-spectrum transceivers offering robust operation in the crowded spectrum. With sophistication in baseband digital signal processing, its increasing interaction with the RF sections, and with increasing experience in simplified radio architectures, all-CMOS radios appear promising in the 900 MHz to 2 GHz bands. A specific CMOS spread-spectrum transceiver project underway at the author's institution is discussed by way of example. >

Low-power radio-frequency ICs for portable communications

The contributions of integrated circuits to the RF front-end of wireless receivers and transmitters operating in broadcast and personnal communications bands are surveyed. It is seen from this that when 1C's enable a rethinking of the RF architecture, the wireless device can sometimes become significantly smaller, and consume much less power. Examples are taken from FM broadcast receiver, pagers, and cellular telephone handsets. Many semiconductor technologies are competing today to supply RF-1C's to cellular telephones. The various design styles and levels of integration are compared, with the conclusion that single-chip silicon transceivers, combined with architectures which substantially reduce off-chip passive components, will likely dominate digital cellular telephones in the near future. The survey also projects future trends for 1C's for miniature spread-spectrum transceivers offering robust operation in the crowded spectrum. With sophistication in baseband digital signal processing, its increasing interaction with the RF sections, and with increasing experience in simolified radio architectures, all-CMOS radios appear promising in the 900 MH z to 2 GH z bands. A specific CMOS spread-spectrum transceiver project underway at the author's institution is discussed by way of example

Low-power radio-frequency IC's for portable communications

A VLSI architecture for an all-digital binary phase shift keying (BPSK) direct-sequence (DS) spread spectrum (SS) intermediate frequency (IF) receiver is presented, and an in-depth performance analysis is given. The all-digital architecture incorporates a Costas loop for carrier recovery and a delay-locked loop for clock recovery. For the pseudorandom noise (PN) acquisition block, a robust energy detection scheme is proposed to reduce false PN locks over a broad range of signal-to-noise ratios. The proposed architecture is intended for use in the 902-928 MHz unlicensed spread spectrum radio band. A 100 kbs information rate and a 12.7 Mchips/second PN code rate are assumed. The IF center frequency is 12.7 MHz and the IF sampling rate is 50.8 Msamples/second, which is the Nyquist rate for the 25.4 MHz bandwidth signal. Finite wordlength effects have been simulated to optimize the architecture, thereby minimizing the chip area, and results of the finite wordlength simulations demonstrate that the chip architecture achieves a bit error rate performance within 1 dB of theory in an additive white Gaussian noise channel. >

Performance analysis of an all-digital BPSK direct-sequence spread-spectrum IF receiver architecture

The design of a binary-phase shift-keyed (BPSK) spread-spectrum chip set with an integrated CAD environment called VANDA is described. VANDA uses the functional compiler concept to integrate system and physical designs, thus allowing complex high-performance integrated circuit chips to be implemented easily. Three functional compilers have been designed and implemented for the design of a spread-spectrum transceiver: a pseudonoise (PN) generator compiler, a direct digital frequency synthesizer (DDFS) compiler, and a Costas loop compiler. Three test chips for a BPSK digital intermediate frequency (IF) spread-spectrum system generated by these compilers have been fabricated and tested. Details of each of the functional compilers and the test chips are described. In addition, the measurement results for digital IF transceiver test boards constructed using these chips are presented. >

Computer-aided design of a BPSK spread-spectrum chip set

The authors describe a design methodology which uses the functional compiler concept to generate the main IF components of a direct sequence binary phase shift keying spread spectrum (DS BPSK SS) transceiver. Three functional compilers are described: a Costas loop generator, a direct digital frequency synthesizer generator, and a Gold sequence pseudorandom number generator. Each compiler automatically generates a digital VLSI implementation for a given set of system specifications. Three 1.2- mu m CMOS chips were automatically generated, fabricated, and tested. These chips form a chip set to be used in a prototype DS BPSK SS transceiver operating at a chip rate of 12.7 MHz and an input data rate of 100 kb/s. >

C. Chien

Papers

Performance analysis of an all-digital BPSK direct-sequence spread-spectrum IF receiver architecture

Computer-aided design of a BPSK spread-spectrum chip set

A direct sequence BPSK spread spectrum transceiver chip set