A sub-1-V CMOS bandgap voltage reference requiring no low threshold voltage device is introduced in this paper. In a CMOS technology with V/sub thn/ /spl ap/ |V/sub thp/| /spl ap/ 0.9 V at 0/spl deg/C, the minimum supply voltage of the proposed voltage reference is 0.98 V, and the maximum supply current is 18 /spl mu/A. A temperature coefficient of 15 ppm//spl deg/C from 0/spl deg/C to 100/spl deg/C is recorded after trimming. The active area of the circuit is about 0.24 mm/sup 2/.

A sub-1-V 15-ppm//spl deg/C CMOS bandgap voltage reference without requiring low threshold voltage device

In this work, a new low-voltage low-power CMOS voltage reference independent of temperature is presented. It is based on subthreshold MOSFETs and on compensating a PTAT-based variable with the gate-source voltage of a subthreshold MOSFET. The circuit, designed with a standard 1.2-/spl mu/m CMOS technology, exhibits an average voltage of about 295 mV with an average temperature coefficient of 119 ppm//spl deg/C in the range -25 to +125/spl deg/C. A brief study of gate-source voltage behavior with respect to temperature in subthreshold MOSFETs is also reported.

A low-voltage low-power voltage reference based on subthreshold MOSFETs

This paper presents an innovative CMOS Bandgap Reference Generator topology that leads to an improved curvature compensation method over a very wide temperature range. The proposed design was implemented in a standard 0.35 μm CMOS process. The compensation is performed by using only poly-silicon resistors. This is achieved by using a second Op-amp that generates a CTAT current, which is subsequently used to enhance the curvature compensation method. The performance of the circuit was verified experimentally. Measured results have shown temperature coefficients as low as 3.9 ppm/°C over a temperature range of 165°C ( -15°C to 150°C ) and temperature coefficients as low as 13.7 ppm/°C over an extended temperature range of 200°C (-50°C to 150°C ). In addition the circuit demonstrated very good line regulation performance for a broad range of supply voltages. The measured line regulation at room temperature is 0.039% V.

A Novel Wide-Temperature-Range, 3.9 ppm/ $^{\circ}$ C CMOS Bandgap Reference Circuit

The design of bandgap-based voltage references in digital CMOS raises several design difficulties, as the supply voltage is lower than the silicon bandgap in electron volts, i.e., 1.2 V. A current-mode architecture is used in order to address the main issues posed by the low supply, but the implementation of the operational amplifier and of dedicated startup circuits deserves some attention. Even if nonstandard devices such as depletion-mode MOS transistors may be helpful to manage the supply scaling, they are seldom available and poorly characterized. Therefore, they must be avoided in a robust design featuring a high portability. This paper proposes some circuit solutions suitable for very low-supply-voltage operation and addresses the main issues of achieving the correct bias point at the power on. A few bandgap references were implemented in digital 0.35- and 0.18-/spl mu/m technologies featuring a nominal output voltage of about 500 mV and minimum supplies from 1.5 to 0.9 V.

/pdf/op-amps-and-startup-circuits-for-cmos-bandgap-references-211pi04gfb.pdf

Op-amps and startup circuits for CMOS bandgap references with near 1-V supply

A CMOS bandgap reference with an inaccuracy of ±0.15% (3 σ) from -40°C to 125°C is presented. In contrast to prior art, it requires only a single trim to achieve this level of precision. A detailed analysis of the various error sources is provided, and techniques to reduce them are discussed. The prototype bandgap reference draws 55 μA from a 1.8 V supply, and occupies 0.12 mm2 in a 0.16 μm CMOS process. Experimental results from two runs show that, with the use of chopping and higher-order curvature correction to remove non-PTAT errors, the residual error of a bandgap reference is mainly PTAT, and can be removed by a single room temperature trim.

A Single-Trim CMOS Bandgap Reference With a $3\sigma$ Inaccuracy of $\pm$ 0.15% From ${-}$ 40 $^{\circ}$ C to 125 $^{\circ}$ C

We present a bandgap circuit capable of generating a reference voltage of 0.53 V. The circuit, implemented In a submicron BiCMOS technology, operates with a supply voltage of 1 V, consuming 92 /spl mu/W at room temperature. In the bandgap circuit proposed, we use a nonconventional operational amplifier which achieves virtually zero systematic offset, operating directly from the 1-V power supply. The bandgap architecture used allows a straightforward implementation of the curvature compensation method. The proposed circuit achieves 7.5 ppm/K of temperature coefficient and 212 ppm/V of supply voltage dependence, without requiring additional operational amplifiers or complex circuits for the curvature compensation.

/pdf/curvature-compensated-bicmos-bandgap-with-1-v-supply-voltage-2g1t6by4d8.pdf

Curvature-compensated BiCMOS bandgap with 1-V supply voltage

In this paper we present a bandgap circuit capable of generating a reference voltage of 0.54 V. The circuit, implemented in a submicron BiCMOS technology, operates with a supply voltage of 1 V. In the bandgap circuit proposed we use a non-conventional operational amplifier which achieves virtually zero systematic offset, operating directly from the 1 V power supply. The bandgap architecture used allows a straightforward implementation of the curvature compensation method. The proposed circuit achieves 5 ppm / K of accuracy without requiring additional operational amplifiers or complex circuits.

/pdf/curvature-compensated-bicmos-bandgap-with-1-v-supply-voltage-3aw4ampv6k.pdf

Curvature compensated BiCMOS bandgap with 1 V supply voltage

The authors describe a phase-locked loop architecture for the locking of nonsinusoidal waveforms. It is based on the generation of the locking signal by means of a proper waveform synthesizer. The free-running frequency of the synthesizer is dynamically adjusted to ensure a suitable lock range. The system has been functionally analyzed and simulated, and its feasibility has been demonstrated. The lock range can extend over more than one decade. The system is suited to implementation using an oversampling approach. The reference waveform is generated with the direct-digital synthesis technique, which obtains the digital representation of the required locking signal by means of a proper ROM. This is converted into a sigma-delta flow by a digital sigma-delta modulator, and is then multiplied by the sigma-delta flow which represents the input signal. The filters and the processing circuits included in the system were realized with digital techniques. >

http://ieeexplore.ieee.org/iel2/640/5940/00230673.pdf

A sigma-delta based PLL for non-sinusoidal waveforms

This paper relies on design strategies for high-speed high-resolution Track and Hold circuits intended as front end of A/D converters for advanced applications. A comparison between two conventional topologies is presented and an analysis of their main non-idealities is carried out. An improved Track and Hold is also presented. It achieves 14 bits of THD with a 40 MHz sinewave sampled at 320 MHz, when a 20 GHz submicron npn bipolar technology is used for simulations. The sampling pedestal error is lower than 100 /spl mu/V.

On the design of high-speed high-resolution track and holds

This paper discusses design issues for high-performance BiCMOS output buffers, as required in T&Hs and data converters for advanced applications. We compare different topologies and analyze the main limitations. The best solution features a linearity better than -105 dB (HD/sub 3/) at an input frequency of 100 MHz. The simulation results referred to a conventional 0.8 /spl mu/m BiCMOS process cover a huge range of performance parameters in terms of linearity, bandwidth and dynamic range. More in general, this paper helps the designer to identify the best strategy for given high speed and high resolution specifications.

/pdf/high-performance-bicmos-output-buffer-design-strategies-4f4jbs5ni9.pdf

C. Fiocchi

Papers

Curvature-compensated BiCMOS bandgap with 1-V supply voltage

Curvature compensated BiCMOS bandgap with 1 V supply voltage

A sigma-delta based PLL for non-sinusoidal waveforms

On the design of high-speed high-resolution track and holds

High-performance BiCMOS output buffer design strategies