C
C.G. Cahill
Researcher at University College Cork
Publications - 6
Citations - 32
C.G. Cahill is an academic researcher from University College Cork. The author has contributed to research in topics: Silicon on insulator & Optimization problem. The author has an hindex of 3, co-authored 6 publications receiving 32 citations.
Papers
More filters
Journal ArticleDOI
Extraction of MOSFET Parameters Using the Simplex Direct Search Optimization Method
TL;DR: The application of the simplex direct search optimization method, in wide use for general optimization problems, needs no derivative calculation and has proved highly stable for MOS model parameter extraction.
Journal ArticleDOI
Materials and devices toward three-dimensional integration
B. Dunne,S. O'Flanagan,L. Hobbs,C.G. Cahill,Alan Mathewson,William Allan Lane,M. Montier,D. Chapuis,Y. Gris,L. Karapiperis,G. Garry,D. Dieumegard,J. L. Regolini,D. Bensahel,J.L. Mermet,H. Cono,H. Achard,J.P. Joly,K. M. Barfoot,M. Field,G. F. Hopper,D. J. Godfrey,P. J. Timans,David J. Smith,D.A. Williams,Richard A. McMahon,M. Ahmed +26 more
TL;DR: In this paper, a two-layer stacked SOI system has been used to produce device quality SOI material and a small test-bed circuit has been designed as a demonstration of the feasibility of this approach.
Journal ArticleDOI
Analysis of distributed resistance effects in MOS transistors
TL;DR: The procedure is used to examine the effect of reduced contact size on standard MOS devices, and results give general guidelines to the extent of the effect are presented.
Proceedings ArticleDOI
Fully stacked 3D devices in electron beam recrystallised material
B. Dunne,S. O'Flanagan,J. Donnelly,C.G. Cahill,Alan Mathewson,P. J. Timans,Richard A. McMahon,Haroon Ahmed +7 more
TL;DR: In this article, a dual-electron-beam recrystallization system was used to form the SOI material for the fabrication of fully stacked devices, where one electron beam was rapidly raster scanned across the underside of the wafer to provide uniform, isothermal heating to a background temperature of 950 degrees C. The second electron beam is incident from above and is formed into a line by scanning with a 100-kHz triangle-wave deflection signal.
Proceedings ArticleDOI
Contribution to 3D SOI integration technologies using seeded laser ZMR and polycide refractory metallisation
H. Achard,J.L. Mermet,H. Bono,J.P. Joly,A. Monroy,D. Chapuis,C.G. Cahill,B. Dunne,Alan Mathewson +8 more
TL;DR: In this paper, the integration of 3-D structures with one-level SOI over bulk is reported, and two kinds of structures have been studied: smart power circuits with bulk LDMOS and laterally displaced CMOS on SOI, and the so-called stacked MOS devices with n or pMOS bulk transistors and the complementary one stacked above using the recrystallized SOI layer.