An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.

Tileable field-programmable gate array architecture

In this paper we present a novel integrated approach to on-line FPGA testing, diagnosis, and fault-tolerance, to be used in high-reliability and high-availability hardware. The test process takes place in self-testing areas (STARs) of the FPGA, without disturbing the normal system operation. The entire chip is eventually tested by having (STARs) gradually rove across the FPGA. Our approach guarantees complete testing of programmable logic blocks and interconnect, and provides maximum diagnostic resolution. A new fault-tolerant (FT) technique allows using partially defective FPGA resources for normal operation, providing longer mission life-span in the presence of faults. We also introduce the basic concepts of a new dynamic FT method, spare resources needed to bypass a fault are always in the neighborhood of the located fault, thus simplifying fault-bypassing.

Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. 

This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

KEY FEATURES
* Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples.
* Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book.
* Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits.
* Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing.
* Practical problems at the end of each chapter for students.

System-on-Chip Test Architectures: Nanometer Design for Testability

In this paper we present an on-line, multi-level fault tolerant (FT) technique for system functions and applications mapped to partially and dynamically reconfigurable FPGAs. Our method is based on the roving self testing areas (STARs) fault detection/location strategy presented in Abramovici et al. (1999). In STARs, the area under test uses partial reconfiguration properties to modify the configuration of the area under test without affecting the configuration of the system function and dynamic reconfiguration properties to allow uninterrupted execution of the system function while reconfiguration takes place. In this paper we take this one step further. Once a fault (or multiple faults) is detected we dynamically reconfigure the working area application around the fault with no additional system function interruption (other than the interruption when a STAR moves to a new location). We also apply the concept of partially usable blocks to increase fault tolerance. Our method has been successfully implemented and demonstrated on the ORCA 2CA series FPGAs from Lucent Technologies.

Dynamic fault tolerance in FPGAs via partial reconfiguration

We present a built-in self-test (BIST) approach able to detect and accurately diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs) with maximum diagnostic resolution. Unlike conventional BIST, FPGA BIST does not involve any area overhead or performance degradation. We also identify and solve the problem of testing configuration multiplexers that was either ignored or incorrectly solved in most previous work. We introduce the first diagnosis method for multiple faulty PLBs; for any faulty PLB, we also identify its internal faulty modules or modes of operation. Our accurate diagnosis provides the basis for both failure analysis used for yield improvement and for any repair strategy used for fault-tolerance in reconfigurable systems. We present experimental results showing detection and identification of faulty PLBs in actual defective FPGAs. Our BIST architecture is easily scalable.

BIST-based test and diagnosis of FPGA logic blocks : Reconfigurable and Adaptive VLSI Systems

We introduce the first BIST approach for testing the programmable routing network in FPGAs. Our method detects opens in, and shorts among, wiring segments, and also faults affecting the programmable switches that configure the FPGA interconnect. As a result, the BIST technique provides complete testing of interconnect faults.

Built-in self-test of FPGA interconnect

Four methods for accessing BIST for FPGAs via the IEEE 1149.1 standard boundary scan interface are presented and discussed in terms of advantages/disadvantages including their impact on test time and diagnostic resolution. These methods can be used in a variety of FPGA architectures for system level testing and diagnosis.

Enhanced BIST-based diagnosis of FPGAs via boundary scan access

Laser Powder bed fusion (L-PBF) has gained much attention for its ability to manufacture high-precision and high-complexity metal components for the aircraft and automobile industries. However, to a certain degree, the print quality (shape, GD&T, mechanical property) is difficult to predict and control due to the multi-variant processability. Recent research predominantly focuses on building a semantic/qualitative process relationship from the single/a few process parameters on the ultimate print qualities, such as thermal distortion failure/defect probabilities. However, such semantic/qualitative process relationships cannot reflect specific governing effects from process variables and provide an optimal selection of the parameters to ensure the build quality. Therefore, there is a strong need to develop a quantitative model within a process network and achieve a constant quality level by controlling the process parameter set. To address the aforementioned challenges, this research focuses on developing a multi-dimensional process-quality interaction model to predict and control the porosity of Titanium 6Al-4V in L-PBF. The process network is first derived from existing literature composing the potential, influential process parameters that can deviate the porosity level, such as laser power and scanning speed. Then the quantitative model is built based on a multi-dimensional quantitative modeling technique from a collection of experimental data. The multi-dimensional modeling provides an architecture that replaces the artificial neural network (ANN) or regression model to depict the mathematical relationship. The established quantitative process models analyze the intercorrelated effects from process parameters to the porosity. The printable zone can also be derived from such a quantitative model and visualized through a multi-dimension variable-control response graph to optimize the selection of process parameters. This would result in a comprehensive understanding of selecting the process parameters according to the desired porosity level and pave the path to fully control the metal L-PBF print qualities by adjusting the process variables. The experimental data also validate the proposed quantitative model to demonstrate its effectiveness and correctness. 

Porosity management and control in powder bed fusion process through process-quality interactions

In this paper we present four methods for accessing BIST for FPGAs via the IEEE 1149.1 standard boundary scan interface along with the advantages and disadvantages of each approach. Each method is evaluated with consideration to test time, logic overhead, diagnostics resolution, usability in FPGAs, and architectural features which would be required to implement the approach. These methods can be used in a variety of FPGA architectures for all levels of testing.

http://ieeexplore.ieee.org/iel5/6211/16590/00766126.pdf

C. Hamilton

Papers

Built-in self-test of FPGA interconnect

Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications

Enhanced BIST-based diagnosis of FPGAs via boundary scan access

Porosity management and control in powder bed fusion process through process-quality interactions

Methods for boundary scan access of built-in self-test for field programmable gate arrays