Proceedings ArticleDOI
Enhanced BIST-based diagnosis of FPGAs via boundary scan access
C. Hamilton,G. Gibson,S. Wijesuriya,Charles E. Stroud +3 more
- pp 413-418
TLDR
Four methods for accessing BIST for FPGAs via the IEEE 1149.1 standard boundary scan interface are presented and discussed in terms of advantages/disadvantages including their impact on test time and diagnostic resolution.Abstract:
Four methods for accessing BIST for FPGAs via the IEEE 1149.1 standard boundary scan interface are presented and discussed in terms of advantages/disadvantages including their impact on test time and diagnostic resolution. These methods can be used in a variety of FPGA architectures for system level testing and diagnosis.read more
Citations
More filters
Proceedings ArticleDOI
Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications
TL;DR: A new fault-tolerant (FT) technique allows using partially defective FPGA resources for normal operation, providing longer mission life-span in the presence of faults, and the basic concepts of a new dynamic FT method are introduced.
Proceedings Article
BIST-based test and diagnosis of FPGA logic blocks : Reconfigurable and Adaptive VLSI Systems
TL;DR: This work introduces the first diagnosis method for multiple faulty PLBs; for any faulty PLB, it is introduced its internal faulty modules or modes of operation and provides the basis for both failure analysis used for yield improvement and for any repair strategy used for fault-tolerance in reconfigurable systems.
Journal ArticleDOI
BIST-based test and diagnosis of FPGA logic blocks
TL;DR: In this article, the authors present a built-in self-test (BIST) approach able to diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs) with maximum diagnostic resolution.
Proceedings ArticleDOI
Roving STARs: an integrated approach to on-line testing, diagnosis, and fault tolerance for FPGAs in adaptive computing systems
TL;DR: This work presents an integrated approach to on-line FPGA testing, diagnosis and fault tolerance, to be used in high-reliability and high-availability hardware and ensures that spare resources are always present in the neighborhood of the located fault, thus simplifying fault-bypassing.
Proceedings ArticleDOI
Novel technique for built-in self-test of FPGA interconnects
TL;DR: This paper presents the first BIST approach for testing interconnects of SRAM-based FPGAs using error control coding, which has superior multiple fault coverage on wire segment stuck-at, stuck-open and bridging faults, programmable switch stuck on/off faults, and the combinations of these faults in global routing resources.
References
More filters
Proceedings ArticleDOI
Built-in self-test of FPGA interconnect
TL;DR: The first BIST approach for testing the programmable routing network in FPGAs is introduced, which detects opens in, and shorts among, wiring segments, and also faults affecting theprogrammable switches that configure the FPGA interconnect.
Proceedings ArticleDOI
BIST-based diagnostics of FPGA logic blocks
TL;DR: This paper presents the first approach able to diagnose faulty programmable logic blocks (PLBs) in Field Programmable Gate Arrays (FPGAs) with maximal diagnostic resolution, based on a new Built-In Self-Test (BIST) architecture for FPGAs and can accurately locate any single and most multiple faulty PLBs.