We might be at the turning point where research in microfluidics undertaken in academia and industrial research laboratories, and substantially sponsored by public grants, may provide a range of portable and networked diagnostic devices. In this Progress Report, an overview on microfluidic devices that may become the next generation of point-of-care (POC) diagnostics is provided. First, we describe gaps and opportunities in medical diagnostics and how microfluidics can address these gaps using the example of immunodiagnostics. Next, we conceptualize how different technologies are converging into working microfluidic POC diagnostics devices. Technologies are explained from the perspective of sample interaction with components of a device. Specifically, we detail materials, surface treatment, sample processing, microfluidic elements (such as valves, pumps, and mixers), receptors, and analytes in the light of various biosensing concepts. Finally, we discuss the integration of components into accurate and reliable devices.

Microfluidic Chips for Point‐of‐Care Immunodiagnostics

Microvascular multinozzle arrays are designed and fabricated for high-throughput printing of functional materials. Ink-flow uniformity within these multigeneration, bifurcating microchannel arrays is characterized by computer modeling and microscopic particle image velocimetry (micro-PIV) measurements. Both single and dual multinozzle printheads are produced to enable rapid printing of multilayered periodic structures over large areas (≈1 m(2)).

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High-throughput printing via microvascular multinozzle arrays.

In an effort to increase processor speeds, 3D IC architecture is being aggressively pursued by researchers and chip manufacturers. This architecture allows extremely high level of integration with enhanced electrical performance and expanded functionality, and facilitates realization of VLSI and ULSI technologies. However, utilizing the third dimension to provide additional device layers poses thermal challenges due to the increased heat dissipation and complex electrical interconnects among different layers. The conflicting needs of the cooling system requiring larger flow passage dimensions to limit the pressure drop, and the IC architecture necessitating short interconnect distances to reduce signal latency warrant paradigm shifts in both of their design approach. Additional considerations include the effects due to temperature nonuniformity, localized hot spots, complex fluidic connections, and mechanical design. This paper reviews the advances in 3D IC cooling in the last decade and provides a vision for codesigning 3D IC architecture and integrated cooling systems. For heat fluxes of 50‐100W/cm 2 on each side of a chip in a 3D IC package, the current single-phase cooling technology is projected to provide adequate cooling, albeit with high pressure drops. For future applications with coolant surface heat fluxes from 100 to 500W/cm 2 , significant changes need to be made in both electrical and cooling technologies through a new level of codesign. Effectively mitigating the high temperatures surrounding local hot spots remains a challenging issue. The codesign approach with circuit, software and thermal designers working together is seen as essential. The through silicon vias (TSVs) in the current designs place a stringent limit on the channel height in the cooling layer. It is projected that integration of wireless network on chip architecture could alleviate these height restrictions since the data bandwidth is independent of the communication lengths. Microchannels that are 200lm or larger in depth are expected to allow dissipation of large heat fluxes with significantly lower pressure drops. [DOI: 10.1115/1.4027175]

Review and Projections of Integrated Cooling Systems for Three-Dimensional Integrated Circuits

In this paper, the electrical-thermal co-simulation of 3D systems with Joule heating, fluidic cooling and air convection effects is proposed. The finite-volume method formulations of voltage distribution equation, heat equations for both fluid flow and solid medium with nonuniform mesh are explained in detail. Based on the proposed iterative co-simulation method, package temperature distribution and voltage drop with Joule heating and fluidic cooling effects can be estimated. Several packaging examples are simulated and the results show that with micro-channel fluidic cooling in high power density 3D integrated packages, the thermal effect on voltage drop is reduced by 10% which is much less than that of using a traditional heat sink.

Electrical-Thermal Co-Simulation of 3D Integrated Systems With Micro-Fluidic Cooling and Joule Heating Effects

Liquid-cooling using microchannel heat sinks etched on silicon dies is seen as a promising solution to the rising heat fluxes in two-dimensional and stacked three-dimensional integrated circuits. Development of such devices requires accurate and fast thermal simulators suitable for early-stage design. To this end, we present 3D-ICE, a compact transient thermal model (CTTM), for liquid-cooled ICs. 3D-ICE was first advanced incorporating the 4-resistor model-based CTTM (4RM-based CTTM). Later, it was enhanced to speed up simulations and to include complex heat sink geometries such as pin fins using the new 2 resistor model (2RM-based CTTM). In this paper, we extend the 3D-ICE model to include liquid-cooled ICs with multi-port cavities, i.e., cavities with more than one inlet and one outlet ports, and non-straight microchannels. Simulation studies using a realistic 3D multiprocessor system-on-chip (MPSoC) with a 4-port microchannel cavity highlight the impact of using 4-port cavity on temperature and also demonstrate the superior performance of 2RM-based CTTM compared to 4RM-based CTTM. We also present an extensive review of existing literature and the derivation of the 3D-ICE model, creating a comprehensive study of liquid-cooled ICs and their thermal simulation from the perspective of computer systems design. Finally, the accuracy of 3D-ICE has been evaluated against measurements from a real liquid-cooled 3D-IC, which is the first such validation of a simulator of this genre. Results show strong agreement (average error ${\bf \lt 10\%}$ ), demonstrating that 3D-ICE is an effective tool for early-stage thermal-aware design of liquid-cooled 2D-/3D-ICs.

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3D-ICE: A Compact Thermal Model for Early-Stage Design of Liquid-Cooled ICs

Power dissipation in microprocessors is projected to reach a level that may necessitate chip-level liquid cooling in the near future. An on-chip microchannel heat sink can reduce the total thermal interfaces between an integrated circuit chip and the convective cooling medium and therefore yield smaller junction-to-ambient thermal resistance. This paper reports the fabrication, assembly, and testing of a silicon chip with complementary metal-oxide-semiconductor process compatible microchannel heat sink and thermofluidic chip input/output (I/O) interconnects fabricated using wafer-level batch processing. Ultra-small form factor, low-cost fabrication and assembly (system integration) are achieved for 2D and 3D chips, as the microchannel heat sink is fabricated directly on back-side of each chip. Through-wafer electrical and fluidic vias are used to interconnect the monolithically integrated microchannel heat sink to thermofluidic chip I/O interconnections. The feasibility of the novel fluidic I/O interconnect is demonstrated through preliminary thermal resistance measurements.

C.R. King

Papers

Integrated Microfluidic Cooling and Interconnects for 2D and 3D Chips