다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Disclosed is an apparatus for use in wireless energy transfer, which includes a first resonator structure configured to transfer energy non-radiatively with a second resonator structure over a distance greater than a characteristic size of the second resonator structure. The non-radiative energy transfer is mediated by a coupling of a resonant field evanescent tail of the first resonator structure and a resonant field evanescent tail of the second resonator structure.

Wireless energy transfer

The electromagnetic energy transfer device includes a first resonator structure receiving energy from an external power supply. The first resonator structure has a first Q-factor. A second resonator structure is positioned distal from the first resonator structure, and supplies useful working power to an external load. The second resonator structure has a second Q-factor. The distance between the two resonators can be larger than the characteristic size of each resonator. Non-radiative energy transfer between the first resonator structure and the second resonator structure is mediated through coupling of their resonant-field evanescent tails.

Wireless non-radiative energy transfer

A 3D-IC technology with integrated microchannel cooling is demonstrated in this paper. Fluidic interconnect network fabrication proceeds at the wafer-level, is compatible with CMOS processing and flip-chip assembly and requires four lithography steps. Measurements for single chips prior to 3D stacking reveal that each die in a two chip 3D stack may potentially exhibit a junction-to-ambient thermal resistance of 0.24°C/W. The demonstrated silicon die contain a through-silicon copper via density of 2500/cm2 integrated within the microchannel heat sink.

A 3D-IC Technology with Integrated Microchannel Cooling

Make way for solutions to the challenges in chip reliability, power delivery, I/O signaling, and heat removal now blocking the way to ultimate performance 3D gigascale SoC. This cutting-edge book on off-chip technologies puts the hottest breakthroughs in high-density compliant electrical interconnects, nanophotonics, and microfluidics at your fingertips, integrating the full range of mathematics, physics, and technology issues together in a single comprehensive source. You get full details on state-of-the-art I/O interconnects and packaging, including mechanically compliant I/O approaches, fabrication, and assembly, followed by the latest advances and applications in power delivery design, analysis, and modeling. The book explores interconnect structures, materials, and packages for achieving high-bandwidth off-chip electrical communication, including optical interconnects and chip-to-chip signaling approaches, and brings you up to speed on CMOS integrated optical devices, 3D integration, wafer stacking technology, and through-wafer interconnects. The volume spells out the latest heat removal technologies including chip-scale microchannel cooling, integrated micropumps and fluidic channels, and various types of carbon nanotube interconnects, along with coverage of wafer-level testing and probe substrates that features probe modules for testing GSI chips. Supported by 100 illustrations and featuring up-to-date physical models and experimental research in all I/O interconnect technologies essential to 3D GSI/TSI realization, this groundbreaking book offers practical guidance to help you achieve next-generation system-on-a-chip performance.

Integrated Interconnect Technologies for 3D Nanoelectronic Systems

Three-dimensional (3D) integration creates vast opportunities to improve performance and the level of integration in nanoelectronic systems. However, 3D integration presents many challenges for power delivery network design due to larger supply currents and longer power delivery paths compared to 2D systems. In this paper, an analytical physical model is derived to incorporate the impact of 3D-integration on power supply noise. The model has less than 4% error compared to SPICE simulations. Based on the model, design guidelines and opportunities for reducing power supply noise, such as inserting "decap" die and through-vias, are discussed in this paper.

Power Delivery for 3D Chip Stacks: Physical Modeling and Design Implication

Power dissipation in microprocessors is projected to reach a level that may necessitate chip-level liquid cooling in the near future. An on-chip microchannel heat sink can reduce the total thermal interfaces between an integrated circuit chip and the convective cooling medium and therefore yield smaller junction-to-ambient thermal resistance. This paper reports the fabrication, assembly, and testing of a silicon chip with complementary metal-oxide-semiconductor process compatible microchannel heat sink and thermofluidic chip input/output (I/O) interconnects fabricated using wafer-level batch processing. Ultra-small form factor, low-cost fabrication and assembly (system integration) are achieved for 2D and 3D chips, as the microchannel heat sink is fabricated directly on back-side of each chip. Through-wafer electrical and fluidic vias are used to interconnect the monolithically integrated microchannel heat sink to thermofluidic chip I/O interconnections. The feasibility of the novel fluidic I/O interconnect is demonstrated through preliminary thermal resistance measurements.

Integrated Microfluidic Cooling and Interconnects for 2D and 3D Chips

This paper describes a novel 3D integration technology that enables the integration of electrical, optical, and microfluidic interconnects in a 3D die stack. The electrical interconnects are used to provide power delivery and signaling, the optical interconnects are used to enable optical signal routing to all levels of the 3D stack, and the microfluidic interconnects are used to cool each level in the 3D stack and thus enable stacking of high-performance (high-power) dice. These interconnects are integrated in a 3D stack both as through-silicon vias (TSVs) and as input/output (I/O) interconnects. Design trade-offs (TSV density, power supply noise, thermal resistance, and pump size), fabrication, and assembly are reported.

Muhannad S. Bakir

Papers

A 3D-IC Technology with Integrated Microchannel Cooling

Integrated Interconnect Technologies for 3D Nanoelectronic Systems

Power Delivery for 3D Chip Stacks: Physical Modeling and Design Implication

Integrated Microfluidic Cooling and Interconnects for 2D and 3D Chips

3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation