International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Methods, systems and devices are described for detecting a position-based attribute of a finger, stylus or other object with a touchpad or other sensor having a touch-sensitive region that includes a plurality of electrodes. Modulation signals for one or more electrodes are produced as a function of any number of distinct digital codes. The modulation signals are applied to an associated at least one of the plurality of electrodes to obtain a resultant signal that is electrically affected by the position of the object. The resultant signal is demodulated using the plurality of distinct digital codes to discriminate electrical effects produced by the object. The position-based attribute of the object is then determined with respect to the plurality of electrodes from the electrical effects.

Methods and systems for detecting a position-based attribute of an object using digital codes

A millimeter-wave absorber based on gallium-substituted epsilon-iron oxide nanomagnets.

In this brief, we introduce the passivity theory into the fault tolerance analysis for switched systems. We propose a ldquoglobal passivityrdquo concept which means that the total energy stored by the switched system is less than the total energy supplied from the outside. The individual passivity of each mode is not required, and the stability of the system can be achieved via the global energy dissipativity in the presence of faults. We further provide a ldquoperiodic fault tolerant passivityrdquo to check the fault tolerance easily. The obtained results are extended to feedback interconnected systems. A switched RLC circuit example is taken to illustrate the efficiency of the proposed results.

Fault Tolerance Analysis for Switched Systems Via Global Passivity

In the deep-submicrometer design regime, RF circuits are expected to be increasingly susceptible to process variations, and thereby suffer from significant loss of parametric yield. To address this problem, a postmanufacture self-tuning technique that aims to compensate for multiparameter variations is presented. The proposed method incorporates a ?response feature? detector and ?hardware tuning knobs,? designed into the RF circuit. The RF device test response to a specially crafted diagnostic test stimulus is logged via the built-in detector and embedded analog-to-digital converter. Analysis and prediction of the optimal tuning knob control values for performance compensation is performed using software running on the baseband DSP processor. As a result, the RF circuit performance can be diagnosed and tuned with minimal assistance from external test equipment. Multiple RF performance parameters can be adjusted simultaneously under tuning knob control. The proposed concepts are illustrated for an RF low-noise amplifier (LNA) design and can be applied to other RF circuits as well. A simulation case study and hardware measurements on a fabricated 1.9-GHz LNAs show significant parametric yield enhancement (up to 58%) across the critical RF performance specifications of interest.

DSP-Driven Self-Tuning of RF Circuits for Process-Induced Performance Variability

The input match of RF front-end circuitry can degrade significantly due to process faults and parasitic package inductances at its input pad. The proposed technique ascertains the input match frequency of the circuit by using a built-in self-test (BiST) structure, determines the frequency interval by which it needs to be shifted to restore it to the desired value, and then feeds back a digital word to the low-noise amplifier (LNA), which adaptively corrects its input-match in real-time. The circuitry presented in the paper offers the advantages of low power overheads (the circuits can be powered off when not in use), robustness, no requirements of digital signal processing cores or processors, and fast calibration times (less than 30 /spl mu/s). This proof of concept is demonstrated by designing a cascode LNA and the complete self-calibration circuit in IBM 0.25-/spl mu/m CMOS RF process.

Self-calibration of input-match in RF front-end circuitry

An input device processing system comprises a sensor module that transmits a first transmitter signal with a transmitter electrode and receives a resulting signal with a receiver electrode. The first transmitter signal comprises a first transmitter frequency, and the resulting signal comprises effects corresponding to the first transmitter signal. A demodulation module demodulates the resulting signal to produce a first signal (e.g., an upper sideband signal) and a second signal (a lower sideband signal), selectably determines a first measurement of a change in capacitive coupling between the transmitter electrode and the receiver electrode based on at least one of the first and second signals, and determines positional information for an input object based on the first measurement.

Systems and methods for signaling and interference detection in sensor devices

This paper presents an ultra-fast built in self test (BiST) approach for RF low noise amplifiers. The technique uses test inputs of moderate precision and low overhead base-band circuitry to quantify various functional specifications in the LNA such as input/output match, power gain and linearity. The total self-test time for all these parameters is 15/spl mu/s, which is several orders of magnitude improvement over existing test techniques. The BiST circuitry described presents low real estate and power overheads and does not require the presence of DSP cores to achieve self-test. The technique has been demonstrated for a 1.9GHz cascode LNA designed in the 0.25 micron IBM 6RF process.

An ultra-fast, on-chip BiST for RF low noise amplifiers

Recent studies have shown that manufacturing costs and design complexities may delay the widespread use of high-κ/metal gate nanoscale CMOS technologies. This implies that traditional (non-high-κ/non-metal gate) ultra-thin oxide technologies will remain active due to economic factors for longer periods of time. Direct tunneling is a significant source of MOSFET gate current in these technologies. Its presence fundamentally alters MOSFET functionality by invalidating the simplifying design assumption of infinite gate resistance. Analog circuit solutions to its problems do not exist in the literature. This paper proposes design solutions that attempt to minimize, balance, and cancel the negative effects of direct tunneling on analog design in traditional ultra-thin oxide CMOS technologies. The proposed solutions re quire only ultra-thin oxide devices and are investigated in a 65-nm CMOS technology with a nominal VDD of 1 V and a physical oxide thickness of 1.25 nm.

Analog IC Design in Ultra-Thin Oxide CMOS Technologies With Significant Direct Tunneling-Induced Gate Current

In this paper, we present the impact of both process and dimensional scaling on input loss (S/sub 11/) prediction of MOSFET's at GHz frequencies. We study the distributed gate effect, the non-quasi static effect, and report a drop in the resistive component of S/sub 11/ for larger fingered devices at high frequencies (> 5 GHz). We identify the boundary at which such effects start dominating. A modification to the existing lumped model is presented that tracks this effect with high accuracy. The impact of oxide thickness on S/sub 11/ in the same process and across two different processes is also presented. The study was validated with the fabrication of an extensive set of RF dimensioned transistors in LSI Logic's 0.18 /spl mu/m and 0.11 /spl mu/m processes, across five different wafers.

C. Washburn

Papers

Self-calibration of input-match in RF front-end circuitry

Systems and methods for signaling and interference detection in sensor devices

An ultra-fast, on-chip BiST for RF low noise amplifiers

Analog IC Design in Ultra-Thin Oxide CMOS Technologies With Significant Direct Tunneling-Induced Gate Current

Effects of technology and dimensional scaling on input loss prediction of RF MOSFETs