Pulse-Doppler radars require high-computing power. A massively parallel machine has been developed in this paper to implement a Pulse-Doppler radar signal processing chain in real-time fashion. The proposed machine consists of two C6678 digital signal processors (DSPs), each with eight DSP cores, interconnected with Serial RapidIO (SRIO) bus. In this study, each individual core is considered as the basic processing element; hence, the proposed parallel machine contains 16 processing elements. A straightforward model has been adopted to distribute the Pulse-Doppler radar signal processing chain. This model provides low latency, but communication inefficiency limits system performance. This paper proposes several optimizations that greatly reduce the inter-processor communication in a straightforward model and improves the parallel efficiency of the system. A use case of the Pulse-Doppler radar signal processing chain has been used to illustrate and validate the concept of the proposed mapping model. Experimental results show that the parallel efficiency of the proposed parallel machine is about 90%.

/pdf/real-time-parallel-implementation-of-pulse-doppler-radar-3xgjsygu4w.pdf

Real-time parallel implementation of Pulse-Doppler radar signal processing chain on a massively parallel machine based on multi-core DSP and Serial RapidIO interconnect

Frequency-modulated pulse trains can be applied in active sonar systems to improve the performance of conventional transmitted waveforms. Recently, two pulse trains have been widely researched as the transmitted waveforms for active sonars. The LFM-Costas pulse train was formed by modulating the linear frequency-modulated (LFM) waveform via the Costas sequence to remove the Doppler ambiguity of LFM pulses. The generalized sinusoidal frequency-modulated (GSFM) waveform, another frequency-modulated pulse train, achieved an ideal ambiguity function shape with thumbtack mainlobe. In this paper, we focus on constructing an optimization model to optimize the LFM-Costas and GSFM pulse trains with the genetic algorithm. The pulse trains can be improved on properties of both ambiguity function and correlations between sub-pulses. The optimized pulse trains are proven to have better detection performance than those of the initial pulse trains, including the lower sidelobe levels of ambiguity function, as well as lower cross-correlation property. Moreover, it is affirmed that the reverberation suppression performance of pulse trains has also been improved through the optimization model.

https://www.mdpi.com/1424-8220/19/19/4262/pdf

Optimal Waveform Design Using Frequency-Modulated Pulse Trains for Active Sonar.

Serial RapidIO is a high-performance, packet-switched that was developed to address the embedded industry's need in term of faster bus speeds, increased bandwidth and reliability. Serial RapidIO allows chip-to-chip and onboard communications. In this paper, we present experimental results on performances optimizations of the Serial RapidIO interconnect integrated in the new digital signal processor (DSP) multi-core TMS320C6474. Our results show that the two transactions Nwrite and Swrite achieve more performances and we determine that in order to transfer a data stream, the interrupt method is the simplest and it increases transfer robustness. The performance difference between the interrupt method and method of EDMA in synchronized mode is tolerable.

Performance optimization of high-speed Interconnect Serial RapidIO for onboard processing

The decades-old memory bottleneck problem for data-intensive applications is getting worse as the processor core counts continue to increase. Workloads with sparse memory access characteristics only achieve a fraction of a system's total memory bandwidth. EMU architecture provides a radical approach to the issue by migrating the computational threads to the location where the data resides. The system enables access to a large PGAS-type memory for hundreds of nodes via a Cilk-based multi-threaded execution scheme. EMU architecture brings brand new challenges in application design and development. Data distribution and thread creation strategies play a crucial role in achieving optimal performance in the EMU platform. In this work, we identify several design considerations that need to be taken care of while developing applications for the new architecture and we evaluate their performance effects on the EMU-chick hardware. We also present a modified BFS algorithm for the EMU system and give experimental results for its execution on the platform.

Designing Algorithms for the EMU Migrating-threads-based Architecture

Software Defined Radio (SDR) has the flexibility to modify the characteristics of the receiving and transmitting radio device, without physically adjusting the hardware, due to development in the system Because of the increasing need for wireless communication applications so as to enable consumers to communicate anywhere through information led to the emergence of many communication devices to include the large amount of applications that every one of the devices needs power and thereby increase the total power This study confirms that the wireless communication system for secured transmit data, fast and inexpensive; can be done by implementing using Partial Reconfiguration (PR) modern technology in FPGA developing based on SDR The Speed and performance can be improved The area also can be decreased The new Xilinx, Vertex Series FPGA, provides the provision of PR The power consumption can be reduced by applying power reduction techniques in the blocks The combination of MATLAB (Simulink and M-file) and Simulink HDL Coder offers flexible capabilities for analysis, design; simulation, implementation, and verification With all these capabilities, in a single system to reduce the time spent tuning for reducing the algorithms and models during rapid prototyping and experimentation and less time on HDL coding

FPGA Implementation of MC-CDMA Wireless Communication System Based on SDR-A Review

Digital down converter (DDC) is the one of the key technologies in the field of software define radio (SDA). Compared with traditional ASIC DDC devices, DDCs implemented by FPGA have more flexible frequency and phase characteristics and higher precision computation. The paper designed and implemented DDC with above advantages on Xilinx FPGA Virtex-5. Through analyzing the key points of DDC theory and MATLAB simulation analysis, DDC with across clock region and FIFO interface characteristics is designed using Xilinx ISE. Some important and practical implementation details are given in this paper. And finally presents one application of DDC in communication systems by the portions given in this document.

Design and FPGA implementation of flexible and efficiency digital down converter

The demand for high-performance embedded signal processing systems has expanded rapidly in recent years. As applications requiring faster computation capability, higher throughput bandwidth and more flexible interconnection, traditional embedded signal processing systems could not meet the demand of ever-increasing performance. The paper designs a high-performance heterogeneous embedded signal processing system based on the serial RapidIO interconnection to fulfill the next generation radar system. The system is designed based from aspects of computation capability of single processor, scale of parallelism in system, arrangement of memory architecture, interconnection topology and bandwidth. The system consists of three modules which are high-speed AD module, heterogeneous processing module including FPGA and CPU and RapidIO switch module. The system conform to Advanced Mezzanine Card (AMC) Standard and AdvancedTCA Standard and all modules aggregated by serial RapidIO. The system can perform up to 2Gsps sampling rate, up to 550MHz processing capability on FPGA and 1.5GHz on CPU and up to 80Gbits/s aggregate bandwidth. And finally applications such as system dataflow and control are presented.

A high-performance heterogeneous embedded signal processing system based on serial RapidIO interconnection

A method using Jakes model is proposed to simply simulate the time-varying UWA channelUsing the delay vector and power vector with Doppler frequency spread information,the time-varying UWA channel with Rayleigh distribution can be simulatedBy comparing BER,demodulation constellation of received signals,and the frequency response between the simulator and the actual shallow sea UWA channel,the model is proved simple and practicable

Time-varying UWA channel with Rayleigh distribution

Two methods to calibrate the sensor positions of the large flexible array had been proposed here Sensor locations uncertainty can severely degrade the performance of directional system after the array had been lied under the sea bottom The two closer sensors of the array were used as the instrumental sensors to estimate DOAs and the elements′ phases at the same time There were at least two sets of calibration data from angularly separated source positions to estimate the sensors positions and the array shape In order to calibrate the array shape correctly, we had compared the two methods through a mount of simulation to find out which one would be more robust while the instrumental sensors were disturbed And the more robust method of MUSIC instrumental sensors method had been used for the data of sea tests from the seatrial

Cai Hui-zhi

Papers

Design and FPGA implementation of flexible and efficiency digital down converter

A high-performance heterogeneous embedded signal processing system based on serial RapidIO interconnection

Time-varying UWA channel with Rayleigh distribution

The calibration of the flexible array′s sensor position based on instrumental sensor method

Orthogonal polyphase code waveforms design using Tabu Search