Showing papers by "Chandra Mouli published in 2014"

Vertical Ferroelectric Field Effect Transistor Constructions, Constructions Comprising A Pair Of Vertical Ferroelectric Field Effect Transistors, Vertical Strings Of Ferroelectric Field Effect Transistors, And Vertical Strings Of Laterally Opposing Pairs Of Vertical Ferroelectric Field Effect Transistors

Abstract: A vertical ferroelectric field effect transistor construction comprises an isolating core A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material Conductive gate material encircles the ferroelectric gate dielectric material The transition metal dichalcogenide material extends elevationally inward and elevationally outward of the conductive gate material A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material Additional embodiments are disclosed

Field effect transistor constructions and memory arrays

Abstract: In some embodiments, a transistor includes a stack having a bottom source/drain region, a first insulative material, a conductive gate, a second insulative material, and a top source/drain region. The stack has a vertical sidewall with a bottom portion along the bottom source/drain region, a middle portion along the conductive gate, and a top portion along the top source/drain region. Third insulative material is along the middle portion of the vertical sidewall. A channel region material is along the third insulative material. The channel region material is directly against the top and bottom portions of the vertical sidewall. The channel region material has a thickness within a range of from greater than about 3 Å to less than or equal to about 10 Å; and/or has a thickness of from 1 monolayer to 7 monolayers.

Apparatuses having a vertical memory cell

Abstract: Methods, apparatuses, and systems for providing a body connection to a vertical access device. The vertical access device may include a digit line extending along a substrate to a digit line contact pillar, a body connection line extending along the substrate to a body connection line contact pillar, a body region disposed on the body connection line, an electrode disposed on the body region, and a word line extending to form a gate to the body region. A method for operation includes applying a first voltage to the body connection line, and applying a second voltage to the word line to cause a conductive channel to form through the body region. A memory cell array may include a plurality of vertical access devices.

Current status and future prospects of non-volatile memory modeling

Abstract: We briefly discuss the evolution of Non-Volatile Memory (NVM) technology in term of macro-trends and their implications for modeling activities in an industrial R&D environment. Some examples of difficult modeling issues for different NVM techologies are mentioned, and finally both present needs and future challanges are critically reviewed.

Semiconductor device structures including energy barriers, and related methods

Abstract: A semiconductor device structure includes a transistor with an energy barrier beneath its transistor channel. The energy barrier prevents leakage of stored charge from the transistor channel into a bulk substrate. Methods for fabricating semiconductor devices that include energy barriers are also disclosed.

Semiconductor isolation structure

Abstract: A method of formation of an isolation structure for vertical semiconductor devices, the resulting isolation structure, and a memory device to prevent leakage among adjacent vertical semiconductor devices are described.

Memory with carbon-containing silicon channel

Abstract: A memory includes a first memory cell and a second memory cell formed over the first memory cell. Each of the first memory cell and the second memory cell includes a channel region comprising silicon and carbon, a control gate, and a dielectric stack between the channel region and the control gate. A carbon content of the channel region of the second memory cell is less than a carbon content of the channel region of the first memory cell.

Semiconductor devices comprising floating gate transistors and methods of forming such semiconductor devices

Abstract: Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an intermediate portion extending between two end portions. The intermediate portion has an average cross-sectional area less than one or both of the end portions. In some embodiments, the intermediate portion may comprise a single nanowire. In additional embodiments, semiconductor devices have one or more transistors having a control gate and a floating gate in which a surface of the control gate opposes a lateral side surface of a floating gate that defines a recess in the floating gate. Electronic systems include such semiconductor devices. Methods of forming semiconductor devices include, for example, forming a floating gate having an intermediate portion extending between two end portions, and configuring the intermediate portion to have an average cross-sectional area less than one or both of the end portions.

Field effect transistor constructions with gate insulator having local regions radially there-through that have different capacitance at different circumferential locations relative to a channel core periphery

Abstract: A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. A gate is proximate a periphery of the channel core. A gate insulator is between the gate and the channel core. The gate insulator has local regions radially there-through that have different capacitance at different circumferential locations relative to the channel core periphery. Additional constructions, and methods, are disclosed.

Apparatus including a capacitor-less memory cell and related methods

Abstract: A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell include forming the capacitor-less memory cell in an active area of a substantially physically isolated portion of a bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.