In one embodiment a non-volatile memory device having improved reliability is formed by oxidizing a first portion of a semiconductor substrate (12) to form a first silicon dioxide layer (14). The first silicon dioxide layer (14) is then annealed and second portion of the silicon substrate, underlying the annealed silicon dioxide layer (16), is then oxidized to form a second silicon dioxide layer (18). The annealed silicon dioxide layer (16) and the second silicon dioxide layer (18) form a pre-oxide layer (20). The pre-oxide layer (20) is then nitrided to form a nitrided oxide dielectric layer (22). A floating gate is then formed overlying the nitrided oxide dielectric layer (22), which serves as the tunnel oxide for the device. Tunnel oxides formed with the inventive process are less susceptible to stress-induced leakage, and therefore, devices with improved data retention and endurance may be fabricated.

Method for forming a semiconductor device having a nitrided oxide dielectric layer

Preparation of Cr-doped Y3Al5O12 phosphors by heterogeneous precipitation methods and their luminescent properties

METHOD OF MAKING EDGE-ALIGNED IMPLANTS AND ELECTRODES THEREFOR Abstract There is disclosed a process particularly suited for making CCD's. The process comprises the steps of a) depositing a layer of conductive material above a semiconductor substrate; b) forming a patterned mask above the con-ductive layer, the pattern exposing spaced-apart strip portions of the conductive layer; c) ion-implanting dopant strips into the sub-strate through the conductive layer strip portions exposed by the patterned mask; d) removing a portion of the mask but retaining the rest so as to expose the conductive layer over first portions of the substrate that contain an implanted dopant strip and over portions of the substrate adjacent to the first portions; e) forming on the conductive layer between the retained mask portions, strips of a material resistant to an etchant for the conductive material; f) removing the retained mask portions; and g) etching away the conductive layer where the latter is not covered with the etchant-resistant mate-rial so as to leave conductive strips overlying the implanted strips.

Method of making edge-aligned implants and electrodes therefor

A semiconductor structure (20) includes a silicon layer (16) formed on an oxide layer (14) Gettering sinks (31, 32) are formed in the silicon layer (16) Lateral gettering is performed to effectively remove impurities from a first section (26) of the semiconductor layer (16) An insulated gate semiconductor device (40) is then formed in semiconductor layer (16), wherein a channel region (55) of the device (40) is formed in the first section (26) of the semiconductor layer (16) A gate dielectric layer (42) of the device (40) is formed over a portion of the first section (26) after the lateral gettering process, thereby enhancing the integrity of the gate dielectric layer (42)

Method for fabricating a semiconductor device using lateral gettering

A command line interface for a data processing system includes an output facility that displays outputs to an operator, a parser that validates inputs entered a command line, a command processor that processes commands validated by the parser. The command line interface preferably supports a prompt mode in which the output facility displays an editable prompt that may be modified by the user to construct a command. In addition, the parser preferably defines separate validation and execution point inputs including at least one validation-only point input, so that inputs are permitted to span multiple input lines and so that atomic sets of commands can be constructed by entering multiple commands on a single input line. The command line interface is also equipped with an in-line help facility that, in response to the parser detecting a help request in a partial command entered at the command line, automatically presents possible input options that can be entered at the command line to complete the partial command.

Command line interface for a data processing system

Copper is shown to be inadvertently introduced as an impurity during the formation of silicon‐on‐insulator structures by high fluence oxygen implantation. Postimplantation annealing causes the copper to diffuse from the silicon surface through the oxide and be preferentially gettered to dislocations that originate at the oxide‐silicon substrate interface. The concentration of copper in the silicon surface layer is reduced by a factor of two, and no copper remains in the buried oxide layer. Sufficient gettering occurs for the fabrication of fully functional n‐channel metal‐oxide‐semiconductor field‐effect‐transistors, with, however, a low yield. Also, the effective carrier mobility in the inversion layer of the transistors is severely degraded, and this is attributed primarily to copper retained in that layer.

Gettering of copper in silicon-on-insulator structures formed by oxygen ion implantation

In an improved method for growing an oxide layer on a silicon surface of a semiconductor body, the semiconductor body is first provided with a silicon surface. A first oxide layer portion is then grown over the silicon surface in a first thermal oxidation process at a temperature of less than about 1000° C. The semiconductor device is then annealed in a nonoxidizing ambient at a temperature above about 1000° C., and finally a second oxide layer portion is then grown over the first oxide layer portion in a second thermal oxidation process to complete the growth of the oxide layer. The silicon surface may be of either polycrystalline or monocrystalline material. This method avoids both the dopant outdiffusion problems associated with present high-temperature oxidation processes and the stress-related irregularities associated with known low-temperature oxidation processes.

Method for growing an oxide layer on a silicon surface

Effect of Dry Etching of a Thermal Oxide on Subsequent Growth and Properties of Thin Oxides (≃ 80 Å)

In an improved method for thermally growing an oxide layer on a silicon surface of a semiconductor body a first oxide layer portion is grown over the silicon surface in a first thermal oxidation process at a temperature of less than about 1000°C. The semiconductor device is then annealed in a nonoxidizing ambient at a temperature above about 1000°C, and finally a second oxide layer portion is then grown over the first oxide layer portion in a second thermal oxidation process to complete the growth of the oxide layer. The silicon surface may be of either polycrystalline or monocrystalline material. This method avoids both the dopant outdiffusion problems associated with present High-temperature oxidation processes and the stress-related irregularities associated with known low-temperature oxidation processes.

Charles Johan Vorst

Papers

Gettering of copper in silicon-on-insulator structures formed by oxygen ion implantation

Method for growing an oxide layer on a silicon surface

Effect of Dry Etching of a Thermal Oxide on Subsequent Growth and Properties of Thin Oxides (≃ 80 Å)

A method for growing an oxide layer on a silicon surface