Metal silicides have played an indispensable role in the rapid developments of microelectronics since PtSi was first used to improve the rectifying characteristics of diodes in early 1960s. This wo ...

Metal silicides in CMOS technology : Past, present, and future trends

Silicides have been a topic of intensive research for more than a decade. The driving force for these investigations has certainly been the interesting materials aspects of the silicides and their applications in integrated circuits. The advantages of easy formability and low resistivity for both CoSi2 and TiSi2 have led to an intensive use of these silicides in self-aligned processes for simultaneous silicidation of source, drain and gate. The fundamental investigations of these silicides include thermodynamic and kinetic aspects of phase formation, interactions with doped Si and related defect generation, and the interaction with oxide and metals. Specific issues related to the technological implementation of silicides in a full process will be discussed in view of the trend to scale the silicided area both in the vertical and in the lateral dimensions.

Silicides for integrated circuits: TiSi2 CoSi2

Preparation of Cr-doped Y3Al5O12 phosphors by heterogeneous precipitation methods and their luminescent properties

The tradeoffs involved in alternative processes for the formation of ultra shallow junctions are described. Low energy implantation, preamorphization to eliminate channeling and low thermal budget processing are adequate to form junctions that are 0.1 to 0.3μm deep. For junctions less than about 100 nm, however, the enhanced diffusion resulting from the amorphization implant reduces its benefits. Athermal diffusion can result in considerable junction motion even when low thermal budget processing is used. Junctions this shallow typically require silicide or metal cladding to reduce the sheet resistance; however, the dopant redistribution associated with siliciding pre-existing junctions increases the contact resistance which diminishes the potential benefit of silicidation. In addition, high leakage can result from excessive silicon consumption. While the use of silicide as a diffusion source can overcome some of the limitations of silicided junctions, this technique can be especially hindered by slow dopant diffusion or compound formation in the silicide and by the limited thermal stability of the silicide. One outstanding issue associated with silicide diffusion sources is understanding the seemingly enhanced diffusivity of dopant in the silicon.

Formation of silicided, ultra-shallow junctions using low thermal budget processing

Incorporation of metal silicides and refractory metals in VLSI technology

CoSi/sub 2/ interconnection layers of 0.14-0.40- mu m thickness were applied in a self-aligned manner to 0.75- mu m-gate-length n-channel and p-channel transistors in a complete CMOS device fabrication flow. The sheet resistance above the active regions ranged from 1.6 to as low as 0.46 Omega /square for the four CoSi/sub 2/ thicknesses examined. Using an Al-Cu/TiW metallization, the resistance per contact for 1- mu m-diameter openings to CoSi/sub 2/ was >

Application of self-aligned CoSi/sub 2/ interconnection in submicrometer CMOS transistors

Copper is shown to be inadvertently introduced as an impurity during the formation of silicon‐on‐insulator structures by high fluence oxygen implantation. Postimplantation annealing causes the copper to diffuse from the silicon surface through the oxide and be preferentially gettered to dislocations that originate at the oxide‐silicon substrate interface. The concentration of copper in the silicon surface layer is reduced by a factor of two, and no copper remains in the buried oxide layer. Sufficient gettering occurs for the fabrication of fully functional n‐channel metal‐oxide‐semiconductor field‐effect‐transistors, with, however, a low yield. Also, the effective carrier mobility in the inversion layer of the transistors is severely degraded, and this is attributed primarily to copper retained in that layer.

Gettering of copper in silicon-on-insulator structures formed by oxygen ion implantation

Ultra-shallow p+/n junctions ( 2 +. Subsequently, low-temperature RTA in N 2 of sputter-deposited Pt produced a 55-nm-thick PtSi layer possessing a remarkably smooth surface and interface, and demonstrating excellent resistance to the aqua regia etch solution. The silicided junctions displayed a sheet resistance of 14 Ω/sq with less than -2-nA . cm-2reverse-bias leakage at -5 V. In a comparative scheme, similar junction characteristics were obtained using a self-aligned 39-nm-thick CoSi 2 overlayer.

Self-aligned silicided (PtSi and CoSi 2 ) ultra-shallow p + /n junctions

The range distributions of 10–120 keV 11B+ in polycrystalline Co, Ti, CoSi2, and TiSi2 targets have been measured by secondary ion mass spectrometry. The obtained projected ranges Rp and projected range stragglings ΔRp are within 25% and 10%, respectively, of those predicted using the Monte Carlo computer program trim. By comparison the one‐dimensional Boltzmann transport calculation in suprem‐3 tends to overestimate Rp by as much as 300% at the highest ion energies.

Range distributions of 11B+ in Co, CoSi2, Ti, and TiSi2

The reverse‐bias leakage of TiSi2/p+‐n Si junctions is <10 nA/cm2 for 0.1‐μm‐deep p+‐Si with a TiSi2 sheet resistance of 1.7 Ω/sq, and is essentially independent of carrier concentration, and the amount of B consumed during silicidation. Forward‐bias current characteristics show that the TiSi2 contacts are ohmic with significant recombination currents and high‐level injection at voltages below the series resistance limit. Post‐silicidation annealing for 30 min at 920 °C, with or without an overlayer of borophosphosilicate glass, increases the majority‐carrier concentration and does not cause B to diffuse out of the Si. Also, minority‐carrier lifetimes show a twofold increase after annealing and this results in nearly ideal junctions with leakage that is dominated by diffusion currents. Thus, TiSi2/p+‐n Si is thermally stable under conditions that are compatible with glass flow and reflow processing.

P. Maillot

Papers

Application of self-aligned CoSi/sub 2/ interconnection in submicrometer CMOS transistors

Gettering of copper in silicon-on-insulator structures formed by oxygen ion implantation

Self-aligned silicided (PtSi and CoSi 2 ) ultra-shallow p + /n junctions

Range distributions of 11B+ in Co, CoSi2, Ti, and TiSi2

Effect of post‐silicidation annealing on TiSi2/p+‐n Si junctions