Featuring higher switching speed and lower losses, the silicon carbide MOSFETs (SiC MOSFETs) are widely used in higher power density and higher efficiency power electronic applications as a new solution. Due to the limited current capability of a single module, more modules parallel-connected are necessary for higher power application. However, current sharing is the key obstacle. In this article, an active gate driver (AGD) for high-power SiC MOSFETs is presented to balance the currents of parallel-connected SiC MOSFET modules. The principle of the AGD is based on dynamic gate drive voltage adjustment to synchronize current edges and current slopes among parallel-connected SiC MOSFET modules automatically. Each AGD measures and controls the current of its SiC MOSFET module individually. No extra supervising control circuit is needed. In addition, the hardware and software configurations are independent of the system design and no restrictions on the number of SiC MOSFET modules connected in parallel exist. Finally, the switching performance of the AGD was experimentally verified on two parallel-connected SiC MOSFET modules in a multipulse test under constant and variable load currents. In addition, the effectiveness of AGD under different control topologies has been studied with simulation and verified using three parallel-connected SiC MOSFET modules.

Active Gate Driver for Improving Current Sharing Performance of Paralleled High-Power SiC MOSFET Modules

Multichip SiC power modules with Kelvin-source connection are popular in applications with large capacity and high switching frequency. However, dynamic current imbalance among paralleled dies due to asymmetric layout limits the available capacity. Thus, this article proposes a method to mitigate the mismatched dynamic current by adjusting the connection points of bonding wires and copper traces. The response surface models and nonlinear constrained optimization algorithms are introduced for the first time to help determine the optimized positions for the connection points. By this method, the dynamic current imbalance can be well suppressed under various working conditions. Besides, the method is cost-efficient and well compatible with the conventional manufacturing technologies because there need no additional efforts but some modifications on bonding wires. At first, the optimization guidelines are obtained after analyzing the mechanism of dynamic current imbalance among paralleled SiC MOSFETs with Kelvin-source connection. Based on the optimization guidelines and response surface models of parasitic inductance, the dynamic current sharing problem can be transformed into a nonlinear constrained optimization issue in mathematics. According to the solution of the mathematic problem, the optimized positions for connection points of bonding wires and copper traces can be determined. Finally, some simulations and experiments are conducted to verify the effectiveness of the proposed method.

A Method to Balance Dynamic Current of Paralleled SiC MOSFETs With Kelvin Connection Based on Response Surface Model and Nonlinear Optimization

Within a power converter, multiple currents are usually measured for control, protection, and/or monitoring. They are therefore important sources of information, which must unquestionably be measured accurately to maintain continuous and reliable operation of the power converter. Accurate current measurement has however become tougher with the introduction of wide band-gap (WBG) devices with switching frequency tending toward the megahertz (MHz) range. Because of that, the installed current sensors must have a significantly widened bandwidth. Moreover, they must be nonintrusive and compact, in order not to degrade fast switching characteristics and high power density of the WBG converter. Presently, these features are not collectively obtainable from existing commercial current sensors. Consequently, many new current sensing techniques have surfaced in the literature for usage with the more demanding MHz power converter. These new techniques, some classical techniques, and their hybrid integrations are now reviewed, after overviewing functionalities made possible by current sensors in a power converter. Last but importantly, some future developmental trends aimed at matching MHz current sensors with MHz power converters are described, before concluding the article.

https://ieeexplore.ieee.org/ielx7/63/9714885/09658157.pdf

A Review of Megahertz Current Sensors for Megahertz Power Converters

Junction temperature is a key parameter for the safe operation of power semiconductor devices in power electronic systems. However, it is difficult to forecast the accurate thermal stress of the device in field use. Consequently, engineers tend to use higher rated devices to maintain excessive margin, resulting in a higher cost. In this article, a transient 3-D thermal modeling method for insulated gate bipolar transistor (IGBT) modules is proposed to obtain accurate temperature distribution considering uneven power losses and cooling conditions. The analytical model of uneven switching energy losses among the parallel IGBT chips in modules is built according to the analysis of device simulation results. The effect of uneven cooling conditions on temperature distribution in IGBT modules is considered by thermal-fluid cosimulation. Furthermore, a hybrid simulation strategy is proposed to obtain the transient thermal behavior in three dimensions. Through appropriate interface design, the power loss model is connected with the finite element model to achieve field-circuit cosimulation with multiple time steps, which takes full consideration of the multiphysical coupling effects among power loss, temperature, and flow fields. Finally, the thermal stresses of IGBT modules under different operating conditions are forecast by the proposed method.

A Transient 3-D Thermal Modeling Method for IGBT Modules Considering Uneven Power Losses and Cooling Conditions

Multiphase inverters (MPIs) continue to increase in popularity owing to their compelling features that include enhanced fault-tolerance capability, improved per-phase power handling, and reduced dc-bus capacitor sizing. This article presents a comprehensive review on MPIs and their application in transportation electrification. More specifically, voltage source inverter (VSI) and nine-switch inverter (NSI) are the two MPI topologies reviewed herein, due to their popularity and potential for employment as traction inverters. The state-of-the-art review covers modeling and control techniques, dc-capacitor sizing, modulation strategies, inverter losses, and cost. Promising future trends of MPIs in terms of topologies, switching devices and integrated design are also investigated.

https://ieeexplore.ieee.org/ielx7/6287639/9668973/09674919.pdf

Multiphase Traction Inverters: State-of-the-Art Review and Future Trends

Parallel connection of silicon carbide (SiC) mosfet s is a popular solution for high-capacity applications. In order to improve the switching speed of paralleled SiC mosfet s, Kelvin-source connection is widely employed. However, the influences of asymmetric layout and unequal junction temperature on current sharing of paralleled SiC mosfet s with Kelvin-source connection are not clear. This article addresses the issue for the first time by theoretical analysis and experimental verifications. The mechanism of current imbalance resulting from asymmetric layout and unequal junction temperature in the case with Kelvin-source connection is comprehensively investigated. Then, some significant discoveries are obtained. The static current sharing performance can be affected by drain and power source parasitic inductance, which is seldom mentioned before. Besides, this article first points out that the effect of power source parasitic inductance on dynamic current sharing is dominant compared with other parasitic inductance. What is more, the thermal–electric analyzing results suggest that there is a risk of thermal runaway for paralleled SiC mosfet s with Kelvin-source connection at high switching frequency due to positively temperature-dependent dynamic current and switching losses. Based on the discoveries, some guidelines are provided for layout design and application of paralleled SiC mosfet s with Kelvin-source connection.

Effect of Asymmetric Layout and Unequal Junction Temperature on Current Sharing of Paralleled SiC MOSFETs With Kelvin-Source Connection

Double-sided cooling based on planar packaging method features better thermal performance than traditional single-sided cooling based on wire bonds. However, this method still faces thermal and electrical challenges in multichip SiC power modules. Specifically, one is severe thermal coupling among parallel bare dies, and the other is unbalanced current sharing due to unreasonable layout design. This article aims to explore the potentials of SiC power devices in power module, which are higher current capability and reliability. The proposed packaging method is called interleaved planar packaging and can get rid of the optimizing contradiction between thermal and electrical performance. In this packaging method, there are two functional units: interleaved switch unit and current commutator structure. Benefited from the two units’ electromagnetic and thermal decoupling effects, the interleaved power module features low loop inductance, balanced current, low coupling thermal resistance, and even thermal distributions. A 1200 V 3.25 mΩ half-bridge SiC power module based on interleaved planar packaging is fabricated and tested to verify this method's superiority.

Interleaved Planar Packaging Method of Multichip SiC Power Module for Thermal and Electrical Performance Improvement

The gallium nitride high electron mobility transistors (GaN HEMTs) are a superior candidate for the new-generation power electronics systems with higher efficiency and power density. However, due to the unique reverse characteristics, the reverse voltage drop of GaN HEMTs is much higher than that of diode. The deadtime loss in GaN-based bridge converters will be comparable to switching losses if the deadtime is not optimized. To optimize the deadtime for higher efficiency, this article proposes an accurate analytical model of GaN HEMTs, including circuit's parasitic inductances, the nonlinear capacitances, the unique reverse characteristics, etc. Taking a GaN-based synchronous buck converter as the example, the proposed model is realized, which fully uses the datasheet to avoid additional experiments. In order to accurately measure the switching current for validation, a novel parasitics-based current measurement method is proposed. The proposed model is verified by simulation in LTspice and experiment, and good agreement is shown. Based on the accurate analytical model, the deadtime is optimized for different load currents to improve the efficiency within the full load range. Compared with the fixed deadtime of 15 ns, the increase of efficiency can be up to 8%. This work will promote the high-frequency application of GaN HEMTs.

Cheng Zhao

Papers

Effect of Asymmetric Layout and Unequal Junction Temperature on Current Sharing of Paralleled SiC MOSFETs With Kelvin-Source Connection

A Method to Balance Dynamic Current of Paralleled SiC MOSFETs With Kelvin Connection Based on Response Surface Model and Nonlinear Optimization

Interleaved Planar Packaging Method of Multichip SiC Power Module for Thermal and Electrical Performance Improvement

An Accurate Datasheet-Based Full-Characteristics Analytical Model of GaN HEMTs for Deadtime Optimization

A Transient 3-D Thermal Modeling Method for IGBT Modules Considering Uneven Power Losses and Cooling Conditions