A new method for forming a dual-metal gate CMOS transistors is described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A nitride layer is deposited overlying a gate dielectric layer and patterned to form a first dummy gate in each of the active areas. First ions are implanted to form source/drain regions in each of the active areas not covered by the first dummy gates. The first dummy gates are isotropically etched to form second dummy gates thinner than the first dummy gates. Second ions are implanted to form lightly doped source/drain regions in each of the active areas not covered by the second dummy gates. Dielectric spacers are formed on sidewalls of the second dummy gates and the source/drain regions are silicided. A dielectric layer is deposited and planarized to the second dummy gates. Thereafter, the second dummy gates are removed, leaving gate openings in the dielectric layer. A mask is formed over the PMOS active area. A first metal layer is deposited in the gate opening in the NMOS active area and planarized to the mask. The mask is removed. A second metal layer is deposited in the gate opening in the PMOS active area. The first and second metal layers are polished away to the dielectric layer thereby completing formation of dual-metal gate CMOS transistors in the fabrication of an integrated circuit.

Method to fabricate dual-metal CMOS transistors for sub-0.1 μm ULSI integration

The present invention facilitates semiconductor fabrication by providing methods of fabrication that mitigate leakage and apply strain to channel regions of transistor devices. A semiconductor device having gate structures, channel regions, and active regions is provided ( 102 ). Extension regions of a first type of conductivity are formed within the active regions ( 104 ). Recesses are then formed within a portion of the active regions ( 106 ). Second type recess structures are formed ( 108 ) within the recesses, wherein the second type recess structures have a second type of conductivity opposite the first type and are comprised of a strain inducing material. Then, first type recess structures are formed ( 110 ) within the recesses and on the second type recess structures, wherein the first type recess structures have the first type of conductivity and are comprised of a strain inducing material.

Systems and methods for low leakage strained-channel transistor

A method of fabricating an integrated circuit with locally confined deep pocket regions utilizes a dummy or sacrificial gate spacer. Dopants are provided through the openings associated with sacrificial spacers to form the pocket regions. The dopants are provided after silicidation. The openings can be filled with spacers. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).

Locally confined deep pocket process for ULSI MOSFETS

The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semiconductor body (12) which is provided with at least one bipolar transistor having an emitter region (1), a base region (2) and a collector region (3), wherein in the semiconductor body (12) a first semiconductor region (13) is formed that forms one (3) of the collector and emitter regions (1,3) and on the surface of the semiconductor body (12) a stack of layers is formed comprising a first insulating layer (4), a polycrystalline semiconductor layer (5) and a second insulating layer (6) in which stack an opening (7) is formed, after which by non-selective epitaxial growth a further semiconductor layer (22) is deposited of which a monocrystalline horizontal part on the bottom of the opening (7) forms the base region (2) and of which a polycrystalline vertical part (2A) on a side face of the opening (7) is connected to the polycrystalline semiconductor layer (5), after which spacers (S) are formed parallel to the side face of the opening (7) and a second semiconductor region (31) is formed between said spacers (S) forming the other one (1) of the emitter and collector regions (1,3). According to the invention the above method is characterized in that before the further semiconductor layer (22) is deposited, the second insulating layer (6) is provided with an end portion (6A) that viewed in projection overhangs an end portion (5A) of the underlying semiconductor layer (5). In this way bipolar transistor devices can be obtained with good high frequency properties in a cost effective manner.

Method of manufacturing a semiconductor device and semiconductor device obtained with such a method

The present invention is related to a method for fabricating a transistor with a polymetal gate electrode structure. The method includes the steps of: forming a gate insulation layer on a substrate; forming a patterned gate stack structure on the gate insulation layer, wherein the patterned stack structure includes a polysilicon layer as a bottom layer and a metal layer as an upper layer; forming a silicon oxide-based capping layer along a profile containing the patterned gate stack structure and on the gate insulation layer at a predetermined temperature that prevents oxidation of the metal layer; and performing a gate re-oxidation process.

Method for fabricating transistor with polymetal gate electrode

The invention provides a gate pocket implantation and post-processing sequence that allows for the creation of a deep and narrow pocket implant without affecting gate threshold voltage and the integrity of the gate oxide layer.

Chia-Hung Tunga

Papers

Integration method for deep sub-micron dual gate transistor design