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Chia-Ling Wei

Researcher at National Cheng Kung University

Publications -  79
Citations -  1080

Chia-Ling Wei is an academic researcher from National Cheng Kung University. The author has contributed to research in topics: CMOS & Boost converter. The author has an hindex of 17, co-authored 76 publications receiving 920 citations. Previous affiliations of Chia-Ling Wei include Silicon Labs & University of Texas System.

Papers
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Design of an Average-Current-Mode Noninverting Buck–Boost DC–DC Converter With Reduced Switching and Conduction Losses

TL;DR: In this article, an average-current-mode noninverting buck-boost dc-dc converter is proposed, which is able to use the full output voltage range of a Li-ion battery, but it also features high power efficiency and excellent noise immunity.
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Nonlinear conductance-volume relationship for murine conductance catheter measurement system

TL;DR: In vitro experiments and numerical model simulations were performed to verify and validate the proposed nonlinear conductance-to-volume conversion equation, which uses a single empirically determined calibration coefficient, derived from independently measured stroke volume.
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Design of a Switched-Capacitor DC-DC Converter With a Wide Input Voltage Range

TL;DR: A triple-mode step-up/step-down switched-capacitor DC-DC converter that can work with a wide input voltage range and a built-in clock generator was designed to generate a constant switching frequency, independent of the input voltage.
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Volume Catheter Parallel Conductance Varies Between End-Systole and End-Diastole

TL;DR: It is proposed that both the capacitive and the resistive properties of the myocardium are substantial, and neither should be ignored, and the measured result should be labeled admittance rather than conductance.
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98.1%-Efficiency Hysteretic-Current-Mode Noninverting Buck–Boost DC-DC Converter With Smooth Mode Transition

TL;DR: In this paper, a hysteretic-current-mode noninverting buck-boost converter with high efficiency and smooth mode transition is proposed, and it was designed and fabricated using TSMC 0.35-μm CMOS 2P4 M 3.3 V/5V mixed-signal polycide process.