This paper presents a 60-GHz direct-conversion transceiver using 60-GHz quadrature oscillators. The transceiver has been fabricated in a standard 65-nm CMOS process. It in cludes a receiver with a 17.3-dB conversion gain and less than 8.0-dB noise figure, a transmitter with a 18.3-dB conversion gain, a 9.5-dBm output 1 dB compression point, a 10.9-dBm saturation output power and 8.8-% power added efficiency. The 60-GHz frequency synthesizer is implemented by a combination of a 20-GHz PLL and a 60-GHz quadrature injection-locked oscillator, which achieves a phase noise of -95 dBc/Hz@l MHz-offset at 60 GHz. The transceiver realizes IEEE802.15.3c full-rate wireless communication for all 16QAM/8PSK/QPSK/BPSK modes, and the communication distances with the full data rate using 2.16-GHz bandwidth, measured with an antenna built in the package, are 2.7-m (BPSK/QPSK) and 0.2-m (8PSK/16QAM). The measured maximum data rates are 8 Gb/s in QPSK mode and 11 Gb/s in 16QAM mode over a 5 cm wireless link within a bit error rate (BER) of <;10-3. The transceiver consumes 186 mW from a 1.2-V supply voltage while transmitting and 106 mW from 1.0-V supply voltage while receiving. Both transmitter and receiver are driven by a 20-GHz PLL, which consumes 66 mW, including output buffer, from a 1.2-V supply voltage.

A 60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE802.15.3c

A clear trend in wireless applications during the last decade has been the push towards higher integration, and multi-mode and multi-band operation, in order to enable low-cost high-functionality consumer devices. As the deployment of silicon-based MMW technology becomes widespread, similar trends may be expected in the MMW space

A Single-Chip Dual-Band 22–29-GHz/77–81-GHz BiCMOS Transceiver

This paper presents the design and characterization of a 0.56 THz frequency synthesizer implemented in standard 65 nm CMOS technology. Its front end consists of triple-push Colpitts oscillators (TPCOs), followed by the first and second stage injection locking frequency dividers (ILFDs) and a divide-by-16 chain. TPCOs are used to triple their fundamental frequencies to 0.53–0.56 THz, while ILFDs and the subsequent divider chain are used to divide such frequencies to 2.7–2.9 GHz. Its back end consists of separate frequency and phase-locked loops with unique CMOS circuit designs to accomplish the desirable frequency/phase locking, including: 1) band-selection inductor switches; 2) simultaneous bulk voltage tuning over TPCOs and the first ILFD; and 3) a dual port injection architecture for the first ILFD. The resultant prototype realizes a 21 GHz frequency locking range with phase noise lower than −74 dBc/Hz at 1 MHz offset, and consumes 174 mW dc power.

A 0.56 THz Phase-Locked Frequency Synthesizer in 65 nm CMOS Technology

This paper presents a 210-GHz amplifier design in 40-nm digital bulk CMOS technology. The theoretical maximum voltage gain that an amplifier can achieve and the loss of a matching network are derived for the optimization of a few hundred gigahertz amplifiers. Accordingly, the bias and size of transistors, circuit topology, and inter-stage coupling method can be determined methodically to maximize the amplifier gain. The measured results show that the amplifier exhibits a peak power gain of 10.5 dB at 213.5 GHz and an estimated 3-dB bandwidth of 13 GHz. The power consumption is only 42.3 mW under a 0.8-V supply. To the best of the authors' knowledge, this work demonstrates the CMOS amplifier with highest operation frequency reported thus far.

https://ir.nctu.edu.tw:443/bitstream/11536/22323/1/000319979300018.pdf

A 210-GHz Amplifier in 40-nm Digital CMOS Technology

D-band (110-170 GHz) injection-locked frequency dividers (ILFDs) using the distributed-LC technique are presented. The input frequency, the locking range, and the design considerations for the D-band ILFDs are analyzed. Six ILFDs are fabricated in 65 nm CMOS process. Two of the ILFDs have locking ranges of 107.9-128.8 GHz and 153.3-162.8 GHz. Each ILFD consumes 6.27 mW from a 1.1 V power supply. The chip area is 0.49 × 0.475-mm2 including the pads. The measurement results conform with the theoretical analysis.

Analysis and Design of D-Band Injection-Locked Frequency Dividers

An injection-locked frequency divider (ILFD) is realized in 65nm CMOS technology for G-band (140 to 220GHz) applications. Its core area is 0.2×0.16mm2. This ILFD consumes 8.8mW from a 1.1V supply excluding the buffers. Due to the limited output power of the source module (i.e., frequency multiplier), the measured locking range of this ILFD is from 198.9GHz to 201.0GHz.

A 198.9GHz-to-201.0GHz injection-locked frequency divider in 65nm CMOS

A divide-by-2 injection-locked frequency divider (ILFD) using π-type LC networks is presented. This ILFD is fabricated in a 65 nm CMOS process. Its measured locking range is from 258.16 to 259.95 GHz with an input power of less than −25 dBm. Its power consumption is 3.9 mW from a 1.3 V supply excluding buffers and the bias current. Its area is 0.13 by 0.12 mm without pads.

258.16-259.95 GHz injection-locked frequency divider

A current-reused divide-by-3 injection-locked frequency divider (ILFD) is realised in a 65 nm CMOS process. This divide-by-3 ILFD achieves the input locking range from 117.45 to 118.38 GHz and its power consumption is 12 mW for a supply of 1.3 V excluding buffers and the biasing circuit. This divide-by-3 ILFD achieves the higher operational frequency and lower power dissipation.

Current-reused divide-by-3 injection-locked frequency divider in 65 nm CMOS

A divide-by-4 injection-locked frequency divider (ILFD) is realized in a 90 nm CMOS process. By using the coupled inductors, the locking range of the proposed divide-by-4 ILFD is enhanced. This ILFD has a measured locking range of 125.7-131.9 GHz. Its power consumption is 3.6 mW for a supply of 1.2 V. To the authors' best knowledge, this is the first CMOS divide-by-4 ILFD operated over 130 GHz.

A 3.6 mW 125.7–131.9 GHz Divide-by-4 Injection-Locked Frequency Divider in 90 nm CMOS

Two 3.6mW D-band divide-by-3 injection-locked frequency dividers (ILFDs) are realized in a 65nm CMOS process. The power consumption is 3.6mW for a supply of 1.2V. By using a second-harmonic enhancement technique, a divide-by-3 ILFD achieves a locking range of 130.01∼132.4GHz. To the authors' best knowledge, this is the first divide-by-3 CMOS ILFD to work at D band.

Chiao-Hsing Wang

Papers

A 198.9GHz-to-201.0GHz injection-locked frequency divider in 65nm CMOS

258.16-259.95 GHz injection-locked frequency divider

Current-reused divide-by-3 injection-locked frequency divider in 65 nm CMOS

A 3.6 mW 125.7–131.9 GHz Divide-by-4 Injection-Locked Frequency Divider in 90 nm CMOS

3.6mW D-band divide-by-3 injection-locked frequency dividers in 65nm CMOS