The Analysis of Time Series: An Introduction, 4th edn. By C. Chatfield. ISBN 0 412 31820 2. Chapman and Hall, London, 1989. 242 pp. £13.50.

The Analysis of Time Series: An Introduction

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Design Of Analog Cmos Integrated Circuits

Due to the unprecedented growth in wireless applications over the past decade, development of low-cost solutions for RF and microwave communication systems has become of great importance. This practical new book is the first comprehensive treatment of lumped elements, which are playing a critical role in the development of the circuits that make these cost-effective systems possible. The books offers you an in-depth understanding of the different types of RF and microwave circuit elements, including inductors, capacitors, resistors, transformers, via holes, airbridges, and crossovers. Supported with over 220 equations and more than 200 illustrations, it covers the practical aspects of each element in exceptional detail. No other single volume treats this subject matter in such depth. From materials, fabrication, and analyses - to design, modeling, and physical, electrical, and thermal applications, this unique resource offers you complete coverage of the critical topics you need understand for your work in the field. Offering the most comprehensive, up-to-date body of knowledge on lumped elements, the book is an indispensable professional reference and serves as an excellent text for senior undergraduate and graduate-level courses in RF and microwave circuit design.

Lumped Elements for RF and Microwave Circuits

A review of recent MOSFET threshold voltage extraction methods

In the paper, an analysis of the state-of-the-art of active elements for analog signal processing is presented which support - in contrast to the conven tional operational amplifiers - not only the voltage-mode but also the current- and mixed-mode operations. Several pro blems are addressed which are associated with the utiliza tion of these elements in linear applications, particularly in frequency filters. A methodology is proposed which generates a number of fundamentally new active elem ents with their potential utilization in various areas o f signal processing.

Active Elements for Analog Signal Processing: Classification, Review, and New Proposals

The authors present a new versatile circuit building block called a differential difference current conveyor (DDCC). An IC technique for implementing the DDCC is also presented. The DDCC-based frequency-selective circuits and nonlinear building blocks such as multiplier, squarer and square rooter are developed. Experimental results are given to demonstrate the feasibility of the proposed techniques, and they show that DDCC-based circuits offer a competitive design choice to CCII-based and DDA-based circuits.

/pdf/cmos-differential-difference-current-conveyors-and-their-3dmi0gt50s.pdf

CMOS differential difference current conveyors and their applications

An ultra-wideband 3.1-10.6-GHz low-noise amplifier employing a broadband noise-canceling technique is presented. By using the proposed circuit and design methodology, the noise from the matching device is greatly suppressed over the desired UWB band, while the noise from other devices performing noise cancellation is minimized by the systematic approach. Fabricated in a 0.18-mum CMOS process, the IC prototype achieves a power gain of 9.7 dB over a -3 dB bandwidth of 1.2-11.9-GHz and a noise figure of 4.5-5.1 dB in the entire UWB band. It consumes 20 mW from a 1.8-V supply and occupies an area of only 0.59 mm2

A Broadband Noise-Canceling CMOS LNA for 3.1–10.6-GHz UWB Receivers

A delay-locked loop (DLL) with wide-range operation and fixed latency of one clock cycle is proposed. This DLL uses a phase selection circuit and a start-controlled circuit to enlarge the operating frequency range and eliminate harmonic locking problems. Theoretically, the operating frequency range of the DLL can be from 1/(N/spl times/T/sub Dmax/) to 1/(3T/sub Dmin/), where T/sub Dmin/ and T/sub Dmax/ are the minimum and maximum delay of a delay cell, respectively, and N is the number of delay cells used in the delay line. Fabricated in a 0.35 /spl mu/m single-poly triple-metal CMOS process, the measurement results show that the proposed DLL can operate from 6 to 130 MHz, and the total delay time between input and output of this DLL is just one clock cycle. From the entire operating frequency range, the maximum rms jitter does not exceed 25 ps. The DLL occupies an active area of 880 /spl mu/m/spl times/515 /spl mu/m and consumes a maximum power of 132 mW at 130 MHz.

A wide-range delay-locked loop with a fixed latency of one clock cycle

A two-stage ultra-wide-band CMOS low-noise amplifier (LNA) is presented. With the common-gate configuration employed as the input stage, the broad-band input matching is obtained and the noise does not rise rapidly at higher frequency. By combining the common-gate and common-source stages, the broad-band characteristic and small area are achieved by using two inductors. This LNA has been fabricated in a 0.18-mum CMOS process. The measured power gain is 11.2-12.4 dB and noise figure is 4.4-6.5 dB with -3-dB bandwidth of 0.4-10 GHz. The measured IIP3 is -6 dBm at 6 GHz. It consumes 12 mW from a 1.8-V supply voltage and occupies only 0.42 mm2

http://web.nchu.edu.tw/~ycchiang/RFIC/CMOS79764430.pdf

An Ultra-Wide-Band 0.4–10-GHz LNA in 0.18- $\mu$ m CMOS

The structure of a miniature three-dimensional (3-D) inductor is presented in this paper. The proposed miniature 3-D inductors have been fabricated in a standard digital 0.35-/spl mu/m one-poly-four-metal (1P4M) CMOS process. According to the measurement results, the self-resonance frequency f/sub SR/ of the proposed miniature 3-D inductor is 34% higher than the conventional stacked inductor. Moreover, the inductor occupies only 16% of the area of the conventional planar spiral inductor with the same inductance and maximum quality factor Q/sub max/. A 2.4-GHz CMOS low-noise amplifier (LNA), which utilized the proposed miniature 3-D inductors, has also been fabricated. By virtue of the small area of the inductor, the size and cost of the radio frequency (RF) chip can be significantly reduced.

https://www.eng.auth.gr/electronicslab/el/vlsi/inductors-apr_2002.pdf?origin=publication_detail

Shen-Iuan Liu

Papers

CMOS differential difference current conveyors and their applications

A Broadband Noise-Canceling CMOS LNA for 3.1–10.6-GHz UWB Receivers

A wide-range delay-locked loop with a fixed latency of one clock cycle

An Ultra-Wide-Band 0.4–10-GHz LNA in 0.18- $\mu$ m CMOS

Miniature 3-D inductors in standard CMOS process