หนงสอเรอง การออกแบบการวจย: วธการวจยเชงคณภาพ วธการวจยเชงปรมาณ และวธการวจยแบบผสม (Research Design: Qualitative, Quantitative, and Mixed Method Approaches) เปนหนงสอทเรยบเรยงเพออธบายเกยวกบความแตกตางของกระบวนทศนการวจยทง 2 แบบ ไดแก การวจย เชงปรมาณ และการวจยเชงคณภาพ และความจำเปนของประเดนปญหาการวจยทตองนำกระบวนทศนทง 2 มารวมกนหาขอคนพบเพอนำไปสผลการวจยทสามารถนำผลการวจยไปใชประโยชนไดอยางจรงมากยงขน เรยกวา “การวจยแบบผสมผสาน” ซงเปนหนงสอทอธบายวธการวจยทง 2 ประเภทไดอยางชดเจน และการรวมกนของกระบวนทศนการวจยทง 2 แบบอยางลงตว

Research Design: Qualitative, Quantitative, and Mixed Method Approaches

Economic Control of Quality of Manufactured Product.

An overview is presented of the current state-of-the-art in silicon nanophotonic ring resonators. Basic theory of ring resonators is discussed, and applied to the peculiarities of submicron silicon photonic wire waveguides: the small dimensions and tight bend radii, sensitivity to perturbations and the boundary conditions of the fabrication processes. Theory is compared to quantitative measurements. Finally, several of the more promising applications of silicon ring resonators are discussed: filters and optical delay lines, label-free biosensors, and active rings for efficient modulators and even light sources.

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Silicon microring resonators

Damascene copper electroplating for on-chip interconnections, a process that we conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition. We discuss here the relationship of additives in the plating bath to superfilling, the phenomenon that results in superconformal coverage, and we present a numerical model which accounts for the experimentally observed profile evolution of the plated metal.

Damascene copper electroplating for chip interconnections

Silicon-on-insulator (SOI) wafers are precisely engineered multilayer semiconductor/dielectric structures that provide new functionality for advanced Si devices. After more than three decades of materials research and device studies, SOI wafers have entered into the mainstream of semiconductor electronics. SOI technology offers significant advantages in design, fabrication, and performance of many semiconductor circuits. It also improves prospects for extending Si devices into the nanometer region (<10 nm channel length). In this article, we discuss methods of forming SOI wafers, their physical properties, and the latest improvements in controlling the structure parameters. We also describe devices that take advantage of SOI, and consider their electrical characteristics.

Frontiers of silicon-on-insulator

The etching of Si, SiO2, Si3N4, and SiCH in fluorocarbon plasmas is accompanied by the formation of a thin steady-state fluorocarbon film at the substrate surface. The thickness of this film and the substrate etch rate have often been related. In the present work, this film has been characterized for a wide range of processing conditions in a high-density plasma reactor. It was found that the thickness of this fluorocarbon film is not necessarily the main parameter controlling the substrate etch rate. When varying the self-bias voltage, for example, we found a weak correlation between the etch rate of the substrate and the fluorocarbon film thickness. Instead, for a wide range of processing conditions, it was found that ion-induced defluorination of the fluorocarbon film plays a major role in the etching process. We therefore suggest that the fluorocarbon film can be an important source of fluorine and is not necessarily an etch-inhibiting film.

Role of fluorocarbon film formation in the etching of silicon, silicon dioxide, silicon nitride, and amorphous hydrogenated silicon carbide

The microloading effect in reactive ion etching

The etch rate of silicon, during reactive ion etching (RIE), depends on the total exposed area. This is called the loading effect. However, local variations in the pattern density will, in a similar way, cause local variations in the etch rate. This effect is caused by a local depletion of reactive species and is called the microloading effect. Silicon wafers patterned with silicon dioxide have been etched in order to study the microloading effect. The pattern consists of a large exposed area and narrow lines at different distances from the edge of the large area. This arrangement makes it possible to study how the distance from the large area, which depletes the etchants, influences the etch rate. The influence of different processing parameters like, e.g., pressure, gas flow rate, and flow direction on the microloading effect have been investigated. It has been found that the microloading effect is small (<10%) compared to other pattern dependent nonuniformities. It is also shown that the nonuniformities caused by the microloading effect can be decreased by, e.g., decreasing the pressure or increasing the gas flow rate.

Microloading effect in reactive ion etching

In this paper we present our in situ, oxygen plasma‐activated wafer bonding process. By keeping one wafer on the anode and the other on the cathode, we have an asymmetric plasma load on the wafers, making our bonding process interesting for low‐temperature applications where damage or defect‐sensitive active layers are bonded to less sensitive carrier wafers. As a step in optimizing the discharge parameters for plasma bonding applications, the effect of the self‐bias voltage on surface energy, oxidation rates, and damage is investigated. An optimum in surface energy was found at moderate self‐bias voltages, both at room temperature bonding and after low‐temperature annealing at 200°C. This is explained by the fact that at these voltages there is a minimum oxide thickness, which promotes the diffusion of water from the bond interface, and also by the fact that at these voltages we have the best surface cleaning conditions. Also, the surface oxide generated by the oxygen plasma seems to be reactive. With our in situ oxygen‐plasma‐activated wafer bonding process there was a major increase in surface energy for wafers bonded at moderate self‐bias volt‐ages compared to conventional wafer bonding performed in ambient air. © 2000 The Electrochemical Society. All rights reserved.

https://iopscience.iop.org/article/10.1149/1.1393592/pdf

Oxidation and Induced Damage in Oxygen Plasma In Situ Wafer Bonding

A limitation in the use of wafer bonding has been the necessity for high-temperature annealing after contacting the wafers at room temperature. In this paper, we try to find the highest surface energy as a function of self-bias voltage in oxygen plasma-activated wafer bonding, in order to achieve a low-temperature bonding process. The bonding was performed in situ the vacuum chamber. It was found that oxygen plasma has a smoothing effect on the surface roughness, rather independent of the plasma self-bias. However, a moderate self-bias voltage proved to give the highest surface energy for the bonded wafers, both at room-temperature and after annealing at 200°C. We believe that this is due to the fact that a moderate self-bias is the most efficient in removing surface contaminants, like water and hydrocarbons. It was also found that even after annealing at higher temperatures, 480°C and 720°C, the plasma-bonded wafers showed higher surface energy values than wafers bonded in ambient air. This investigation was focused on low-effect plasmas,

Christer Hedlund

Papers

Role of fluorocarbon film formation in the etching of silicon, silicon dioxide, silicon nitride, and amorphous hydrogenated silicon carbide

The microloading effect in reactive ion etching

Microloading effect in reactive ion etching

Oxidation and Induced Damage in Oxygen Plasma In Situ Wafer Bonding

Surface energy as a function of self-bias voltage in oxygen plasma wafer bonding