The ever increasing requirements for electrical performance of on-chip wiring has driven three major technological advances in recent years. First, copper has replaced Aluminum as the new interconnect metal of choice, forcing also the introduction of damascene processing. Second, alternatives for SiO2 with a lower dielectric constant are being developed and introduced in main stream processing. The many new resulting materials needs to be classified in terms of their materials characteristics, evaluated in terms of their properties, and tested for process compatibility. Third, in an attempt to lower the dielectric constant even more, porosity is being introduced into these new materials. The study of processes such as plasma interactions and swelling in liquid media now becomes critical. Furthermore, pore sealing and the deposition of a thin continuous copper diffusion barrier on a porous dielectric are of prime importance. This review is an attempt to give an overview of the classification, the character...

Low dielectric constant materials for microelectronics

Modern computer microprocessor chips are marvels of engineering complexity. For the current 45 nm technology node, there may be nearly a billion transistors on a chip barely 1 cm2 and more than 10 000 m of wiring connecting and powering these devices distributed over 9-10 wiring levels. This represents quite an advance from the first INTEL 4004B microprocessor chip introduced in 1971 with 10 μm minimum dimensions and 2 300 transistors on the chip! It has been disclosed that advanced microprocessor chips at the 32 nm node will have more than 2 billion transistors.1 For instance, Figure 1 shows a sectional 3D image of a 90 nm IBM microprocessor, containing several hundred million integrated devices and 10 levels of interconnect wiring, designated as the back-end-of-the-line (BEOL). Since the invention of microprocessors, the number of active devices on a chip has been exponentially increasing, approximately doubling every two years. This trend was first described in 1965 by Gordon Moore,2 although the original discussion suggested doubling the number of devices every year, and the phenomenon became popularly known as Moore’s Law. This progress has proven remarkably resilient and has persisted for more than 50 years. The enabler that has permitted these advances is known as scaling, that is, the reduction of minimum device dimensions by lithographic advances (photoresists, tooling, and process integration optimization) by ∼30% for each device generation.3 It allowed more active devices to be incorporated in a given area and improved the operating characteristics of the individual transistors. It should be emphasized that the earlier improvements in chip performance were achieved with very few changes in the materials used in the construction of the chips themselves. The increase of performance with scaling * Corresponding author. E-mail: gdubois@us.ibm.com. † IBM Almaden Research Center. ‡ Stanford University. Willi Volksen received his B.S. in Chemistry (magna cum laude) from New Mexico Institute of Mining and Technology in 1972 and his Ph.D. in Chemistry/Polymer Science from the University of Massachusetts, Lowell, in 1975. He then joined the research group of Prof. Harry Gray/Dr. Alan Rembaum at the California Institute of Technology as a postdoctoral fellow and upon completion of the one-year appointment joined Dr. Rembaum at the Jet Propulsion Laboratory as a Senior Chemist in 1976. In 1977 Dr. Volksen joined the IBM Research Division at the IBM Almaden Research Center in San Jose, CA, where he is an active research staff member in the Advanced Materials Group of the Science and Technology function.

Low dielectric constant materials.

High aspect ratio (HAR) silicon etch is reviewed, including commonly used terms, history, main applications, different technological methods, critical challenges, and main theories of the technologies. Chronologically, HAR silicon etch has been conducted using wet etch in solution, reactive ion etch (RIE) in low density plasma, single-step etch at cryogenic conditions in inductively coupled plasma (ICP) combined with RIE, time-multiplexed deep silicon etch in ICP-RIE configuration reactor, and single-step etch in high density plasma at room or near room temperature. Key specifications are HAR, high etch rate, good trench sidewall profile with smooth surface, low aspect ratio dependent etch, and low etch loading effects. Till now, time-multiplexed etch process is a popular industrial practice but the intrinsic scalloped profile of a time-multiplexed etch process, resulting from alternating between passivation and etch, poses a challenge. Previously, HAR silicon etch was an application associated primarily with microelectromechanical systems. In recent years, through-silicon-via (TSV) etch applications for three-dimensional integrated circuit stacking technology has spurred research and development of this enabling technology. This potential large scale application requires HAR etch with high and stable throughput, controllable profile and surface properties, and low costs.

High aspect ratio silicon etch: A review

The field of plasma etching is reviewed. Plasma etching, a revolutionary extension of the technique of physical sputtering, was introduced to integrated circuit manufacturing as early as the mid 1960s and more widely in the early 1970s, in an effort to reduce liquid waste disposal in manufacturing and achieve selectivities that were difficult to obtain with wet chemistry. Quickly, the ability to anisotropically etch silicon, aluminum, and silicon dioxide in plasmas became the breakthrough that allowed the features in integrated circuits to continue to shrink over the next 40 years. Some of this early history is reviewed, and a discussion of the evolution in plasma reactor design is included. Some basic principles related to plasma etching such as evaporation rates and Langmuir–Hinshelwood adsorption are introduced. Etching mechanisms of selected materials, silicon, silicon dioxide, and low dielectric-constant materials are discussed in detail. A detailed treatment is presented of applications in current silicon integrated circuit fabrication. Finally, some predictions are offered for future needs and advances in plasma etching for silicon and nonsilicon-based devices.

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Plasma etching: Yesterday, today, and tomorrow

On-chip optical resonators have the promise of revolutionizing numerous fields, including metrology and sensing; however, their optical losses have always lagged behind those of their larger discrete resonator counterparts based on crystalline materials and silica microtoroids. Silicon nitride (Si3N4) ring resonators open up capabilities for frequency comb generation, optical clocks, and high-precision sensing on an integrated platform. However, simultaneously achieving a high quality factor (Q) and high confinement in Si3N4 (critical for nonlinear processes, for example) remains a challenge. Here we show that addressing surface roughness enables overcoming the loss limitations and achieving high-confinement on-chip ring resonators with Q of 37 million for a ring of 2.5 μm width and 67 million for a ring of 10 μm width. We show a clear systematic path for achieving these high Qs, and these techniques can also be used to reduce losses in other material platforms independent of geometry. Furthermore, we demonstrate optical parametric oscillation using the 2.5 μm wide ring with sub-milliwatt pump powers and extract the loss limited by the material absorption in our films to be 0.13±0.05  dB/m, which corresponds to an absorption-limited Q of at least 170 million by comparing two resonators with different degrees of confinement. Our work provides a chip-scale platform for applications such as ultralow-power frequency comb generation, laser stabilization, and sideband-resolved optomechanics.

Ultra-low-loss on-chip resonators with sub-milliwatt parametric oscillation threshold

The mechanisms underlying selective etching of a SiO2 layer over a Si or Si3N4 underlayer, a process of vital importance to modern integrated circuit fabrication technology, has been studied. Selective etching of SiO2-to-Si3N4 in various inductively coupled fluorocarbon plasmas (CHF3, C2F6/C3F6, and C3F6/H2) was performed, and the results compared to selective SiO2-to-Si etching. A fluorocarbon film is present on the surfaces of all investigated substrate materials during steady state etching conditions. A general trend is that the substrate etch rate is inversely proportional to the thickness of this fluorocarbon film. Oxide substrates are covered with a thin fluorocarbon film (<1.5 nm) during steady-state etching and at sufficiently high self-bias voltages, the oxide etch rates are found to be roughly independent of the feedgas chemistry. The fluorocarbon film thicknesses on silicon, on the other hand, are strongly dependent on the feedgas chemistry and range from ∼2 to ∼7 nm in the investigated process...

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Study of the SiO2-to-Si3N4 etch selectivity mechanism in inductively coupled fluorocarbon plasmas and a comparison with the SiO2-to-Si mechanism

It has been found that in the etching of SiO2 using CHF3 in an inductively coupled plasma reactor of the planarized coil design, a thin steady state fluorocarbon film can play an important role in determining the rate of etching. This etching is encountered as the amount of bias power used in the SiO2 etching process is increased, and a transition from fluorocarbon film growth on the SiO2 to an oxide etching rate which is consistent with reactive sputtering theory is made. The observed presence of an intermediate region where etching occurs, although a steady state fluorocarbon film suppresses the etch rate from that expected for a reactive sputtering process, has been referred to as the fluorocarbon suppression regime. This work demonstrates the role of the steady state fluorocarbon film present on silicon dioxide during etching within the fluorocarbon suppression regime. X-ray photoelectron spectroscopy studies of the surfaces of partially etched SiO2 have shown a thinning of this film with increasing r...

Role of steady state fluorocarbon films in the etching of silicon dioxide using CHF3 in an inductively coupled plasma reactor

For various fluorocarbon processing chemistries in an inductively coupled plasma reactor, we have observed relatively thick (2–7 nm) fluorocarbon layers that exist on the surface during steady state etching of silicon. In steady state, the etch rate and the surface modifications of silicon do not change as a function of time. The surface modifications were characterized by in situ ellipsometry and x-ray photoelectron spectroscopy. The contribution of direct ion impact on the silicon substrate to the etching mechanism is reduced with increasing fluorocarbon layer thickness. Therefore, we consider that the silicon etch rate is controlled by a neutral etchant flux through the layer. Our experimental data show, however, that ions play an import role in the transport of silicon etching precursors through the layer. A model is developed that describes the etch kinetics through a fluorocarbon layer based on a fluorine diffusion transport mechanism. The model is consistent with the data when one or two of the fol...

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High density fluorocarbon etching of silicon in an inductively coupled plasma: Mechanism of etching through a thick steady state fluorocarbon layer

The etching of Si, SiO2, Si3N4, and SiCH in fluorocarbon plasmas is accompanied by the formation of a thin steady-state fluorocarbon film at the substrate surface. The thickness of this film and the substrate etch rate have often been related. In the present work, this film has been characterized for a wide range of processing conditions in a high-density plasma reactor. It was found that the thickness of this fluorocarbon film is not necessarily the main parameter controlling the substrate etch rate. When varying the self-bias voltage, for example, we found a weak correlation between the etch rate of the substrate and the fluorocarbon film thickness. Instead, for a wide range of processing conditions, it was found that ion-induced defluorination of the fluorocarbon film plays a major role in the etching process. We therefore suggest that the fluorocarbon film can be an important source of fluorine and is not necessarily an etch-inhibiting film.

Role of fluorocarbon film formation in the etching of silicon, silicon dioxide, silicon nitride, and amorphous hydrogenated silicon carbide

The influence of reactor wall conditions on the characteristics of high density fluorocarbon plasma etch processes has been studied. Results obtained during the etching of oxide, nitride, and silicon in an inductively coupled plasma source fed with various feedgases, such as CHF3, C3F6, and C3F6/H2, indicate that the reactor wall temperature is an important parameter in the etch process. Adequate temperature control can increase oxide etch selectivity over nitride and silicon. The loss of fluorocarbon species from the plasma to the walls is reduced as the wall temperature increased. The fluorocarbon deposition on a cooled substrate surface increases concomitantly, resulting in a more efficient suppression of silicon and nitride etch rates, whereas oxide etch rates remain nearly constant.

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T. E. F. M. Standaert

Papers

Study of the SiO2-to-Si3N4 etch selectivity mechanism in inductively coupled fluorocarbon plasmas and a comparison with the SiO2-to-Si mechanism

Role of steady state fluorocarbon films in the etching of silicon dioxide using CHF3 in an inductively coupled plasma reactor

High density fluorocarbon etching of silicon in an inductively coupled plasma: Mechanism of etching through a thick steady state fluorocarbon layer

Role of fluorocarbon film formation in the etching of silicon, silicon dioxide, silicon nitride, and amorphous hydrogenated silicon carbide

Influence of reactor wall conditions on etch processes in inductively coupled fluorocarbon plasmas