Showing papers by "Christian Landrault published in 1996"

A diagnostic ATPG for delay faults based on genetic algorithms

Abstract: This paper presents a GA-based technique to generate diagnostic-oriented delay tests for logic circuits. The aim is to produce a test sequence for a given circuit such that any couple of non-equivalent delay faults is distinguished by at least one rest pair belonging to the test sequence. For this purpose, we decided to preferably use a simulation-based approach with a directed search mechanism rather than developing a new deterministic ATPG. An appropriate fitness function that ranks population members according to their diagnostic capabilities has been defined, and genetic operators allowing a population to evolve during successive generations are presented. In order to have a diagnostic program providing near-optimal solutions, we combined the GA-based technique proposed in this paper with an existing post test diagnostic method for delay faults. Experimental results show that the genetic approach is effective for solving our diagnostic test generation problem, and point out the fact that the GA performs very well in comparison to a random test method.

A new test pattern generation method for delay fault testing

Abstract: Importance of delay testing is growing especially for high speed circuits. As delay testing using automatic test equipment is expensive, built-in self-test is an alternative technique that can significantly reduce the cost of delay testing. In this paper a new test pattern generation method for the detection of delay faults is proposed. It can be seen as a directed random generation technique, and uses some original concepts from machine learning to generate delay fault detecting test pairs. First, a set of random test vectors is generated. Next, a learning tool working on those vectors provides relevant features of delay fault detecting test pairs. Finally, a set of new test vectors that are consistent with those features is generated. A comparison with other test generation techniques has been done on several circuits, and has shown the efficiency of our solution in terms of test sequence length and delay fault coverage.

DFSIM: a gate-delay fault simulator for sequential circuits

Abstract: This paper addresses the problem of simulating gate delay faults in synchronous sequential circuits and presents the solution implemented in the fault simulator DFSIM. In sequential circuits, the fault simulation problem is mainly the propagation of the fault effects through the flip-flops. As different fault sizes may result in different faulty circuit behaviors, dealing with the size of faults during fault propagation is required to provide exact and accurate results. However, due to the high computational complexity, it is not possible to divide fault sizes into fine-grained ranges and simulate each of them separately. In this paper we propose a method for simulating gate delay faults in sequential circuits which is capable of dealing with the size of faults. The solution to the fault simulation problem is obtained by handling the fault size implicitly, rather than explicitly, through a detection range calculation process.