Showing papers by "Christian Landrault published in 1999"

On calculating efficient LFSR seeds for built-in self test

Abstract: Linear Feedback Shift Registers (LFSRs) are commonly used as pseudo-random test pattern generators (TPGs) in BIST schemes. This paper presents a fast simulation-based method to compute an efficient seed (initial state) of a given primitive polynomial LFSR TPG. The size of the LFSR, the primitive feedback polynomial and the length of the generated test sequence are a priori known. The method uses a deterministic test cube compression technique and produces a one-seed LFSR test sequence of a predefined test length that achieves high fault coverage. This technique can be applied either in pseudo-random testing for BISTed circuits containing few random resistant faults, or in pseudo-deterministic BIST where it allows the hardware generator overhead area to be reduced. Compared with existing methods, the proposed technique is able to deal with combinational circuits of great size and with a lot of primary inputs. Experimental results demonstrate the effectiveness of our method.

Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity

Abstract: Low-power design looks for low-energy BIST. This paper considers the problem of minimizing the energy required to test a BISTed combinational circuit without modifying the stuck-at fault coverage and with no extra area or delay overhead over the classical LFSR architectures. The objective of this paper is twofold. First, is to analyze the impact of the polynomial and seed selection of the LFSR used as TPG on the energy consumed by the circuit. It is shown that appropriately selecting the seed of the LFSR can lead to an important energy reduction. Second, is to propose a method to significantly decrease the energy consumption of BIST sessions. For this purpose, a heuristic method based on a simulated annealing algorithm is briefly described in this paper. Experimental results using the ISCAS benchmark circuits are reported, showing variations of the weighted switching activity ranging from 147% to 889% according to the seed selected for the LFSR. Note that these results are always obtained with no loss of stuck-at fault coverage.

A test vector ordering technique for switching activity reduction during test operation

Abstract: This paper considers the problem of testing VLSI integrated circuits without exceeding their power ratings during test. The proposed approach is based on the reordering of test vectors of a given test sequence to minimize the average and peak power dissipation during test operation. For this purpose, the proposed technique reduces the internal switching activity by lowering the transition density at circuit inputs. The technique considers combinational or full scan sequential circuits and do not modify the initial fault coverage. Results of experiments show reductions of the switching activity ranging from 11% to 66% during external test application.

Circuit partitioning for low power BIST design with minimized peak power consumption

Abstract: In this paper, we propose a novel low power/energy built-in self test (BIST) strategy based on circuit partitioning. The goal of the proposed strategy is to minimize the average power, the peak power and the energy consumption during pseudo-random testing without modifying the fault coverage. The strategy consists in partitioning the original circuit into two structural subcircuits so that each subcircuit can be successively tested through two different BIST sessions. In partitioning the circuit and planning the test session, the switching activity in a time interval (i.e. the average power) as well as the peak power consumption are minimized. Moreover, the total energy consumption during BIST is also reduced since the test length required to test the two subcircuits is roughly the same as the test length for the original circuit. Results on ISCAS circuits show that average power reduction of up to 72%, peak power reduction of up to 53%, and energy reduction of up to 84% can be achieved.

A Scan-BIST Structure to Test Delay Faults in Sequential Circuits

Abstract: Delay testing that requires the application of consecutive two-pattern tests is not an easy task in a scan-based environment. This paper proposes a novel approach to the delay fault testing problem in scan-based sequential circuits. This solution is based on the combination of a BIST structure with a scan-based design to apply delay test pairs to the circuit under test.

Partial set for flip-flops based on state requirement for non-scan BIST scheme

Abstract: This paper describes a methodology for improving sequential circuit's testability in a pseudo-random testing environment Our goal is to slightly modify the circuit under test with a DFT technique For this, partial reset of circuit's flip-flops is performed during application of the test sequence Flip-flop candidates far reset and their reset period are chosen according to a methodology based on identification of required test states for hard-to-detect faults By increasing the probability to reach these states, we improve the fault coverage

Efficient 3D modelling for extraction of interconnect capacitances in deep submicron dense layouts

Abstract: This paper introduces a set of analytical formulations for 3D modelling of inter-layer capacitances. Efficiency and accuracy are both guaranteed by the process characterization approach. Analytical modelling of interconnect capacitances is then demonstrated to be an helpful alternative to lookup tables or numerical simulations.