Showing papers by "Christian Landrault published in 2003"
30 Sep 2003
TL;DR: A new technique is presented that allows to design power-optimized scan chains under a given routing constraint based on clustering and reordering of scan cells in the design and allows to reduce average power consumption during scan testing.
Abstract: Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized scan chains under a given routing constraint. The proposed technique is a three-phase process based on clustering and reordering of scan cells in the design. It allows to reduce average power consumption during scan testing. Owing to this technique, short scan connections in scan chains are guaranteed and congestion problems in the design are avoided.
90 citations
TL;DR: A new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under test (CUT), i.e., no test point insertion is presented.
Abstract: This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under test (CUT), i.e., no test point insertion. The set of patterns generated by a pseudo-random pattern generator, e.g. a Linear Feedback Shift Register (LFSR), is transformed into a new set of patterns that provides the desired fault coverage. To transform these patterns, a ring architecture composed by a set of masks is used. During on-chip test pattern generation, each mask is successively selected to map the original pattern sequence into a new test sequence. We describe an efficient algorithm that constructs a ring of masks from the test cubes provided by an automatic test pattern generator (ATPG) tool. Moreover, we show that rings of masks are implemented very easily at low silicon area cost, without requiring any logic synthesis tool; a combinational mapping logic corresponding to the masks is placed between the LFSR and the CUT, together with a looped shift register that acts as a mask selecting circuit. Experimental results are given at the end of the paper, demonstrating the effectiveness of the proposed approach in terms of area overhead, fault coverage and test sequence length. Note that this paper is an extended version of [1].
20 citations
17 Sep 2003
TL;DR: This paper first survey the recent approaches proposed for minimizing test power, and proposes some interesting directions for the development of new low power testing techniques by enumerating the relevant criteria that have to be satisfied.
Abstract: Test power relates to the power consumed during test of integrated circuits or embedded cores. Test power is now a big concern in large System-on-Chip designs. In this paper, we propose to shortly review the state-of-the-art in this domain. We first survey the recent approaches proposed for minimizing test power. Next, we propose some interesting directions for the development of new low power testing techniques by enumerating the relevant criteria that have to be satisfied.
3 citations
TL;DR: The partial reset technique is used to improve hard-to-detect fault activation and this DFT approach is completed with classical insertion of observation points in order to improve fault propagation.
Abstract: This paper presents a partial reset technique for testability improvement of non-scan sequential circuits. Both pseudo-random BIST and deterministic External Test are in the scope of this paper. The partial reset technique is used to improve hard-to-detect fault activation. This DFT approach is completed with classical insertion of observation points in order to improve fault propagation. Numerous experimental results on ISCAS'89 benchmark circuits show that 100% fault efficiency can be achieved at low cost.
2 citations