This brief proposes a novel circuit architecture of an 11-bit reversible successive approximation register (RSAR)controlled all-digital delay-locked loop (DLL), which could achieve adaptive bandwidth in a wide operation range by utilizing the modified binary search algorithm of the RS AR scheme. Moreover, it is fast locking because it finds the suitable delay range first and the successive approximation register process next. The proposed RSAR DLL is fabricated into a 0.2 × 0.1 mm2 silicon with SMIC 0.13-μm 1P6M complimentary metal-oxide-semiconductor technology. Test shows that the chip could work in a wide frequency range from 30 MHz to 1 GHz, with less than 42 cycles lock-in time, 10-ps delay resolution, and 1.5 mW at 30-MHz power dissipation.

An Implementation of Fast-Locking and Wide-Range 11-bit Reversible SAR DLL

The recently proposed NAND-based digitally controlled delay-lines (DCDL) present a glitching problem which may limit their employ in many applications. This paper presents a glitch-free NAND-based DCDL which overcame this limitation by opening the employ of NAND-based DCDLs in a wide range of applications. The proposed NAND-based DCDL maintains the same resolution and minimum delay of previously proposed NAND-based DCDL. The theoretical demonstration of the glitch-free operation of proposed DCDL is also derived in the paper. Following this analysis, three driving circuits for the delay control-bits are also proposed. Proposed DCDLs have been designed in a 90-nm CMOS technology and compared, in this technology, to the state-of-the-art. Simulation results show that novel circuits result in the lowest resolution, with a little worsening of the minimum delay with respect to the previously proposed DCDL with the lowest delay. Simulations also confirm the correctness of developed glitching model and sizing strategy. As example application, proposed DCDL is used to realize an All-digital spread-spectrum clock generator (SSCG). The employ of proposed DCDL in this circuit allows to reduce the peak-to-peak absolute output jitter of more than the 40% with respect to a SSCG using three-state inverter based DCDLs.

Glitch-Free NAND-Based Digitally Controlled Delay-Lines

This paper presents the design of a new ADDLL for clock synchronization in a SoC, regardless if the clock duty cycle is seriously distorted from 50%. A half-delay-line circuit and an improved successive-approximation-register controller are developed on top of the coarse-fine architecture for fast lock-in, high duty-cycle-distortion tolerant, and low power. Difference-type circuits and the design techniques for reducing the number of active delay cells and suppressing the dithering effect are developed for low jitter. Measurement results show that when operated at 1.0 V, the 55 nm ADDLL has a maximal frequency of 850 MHz with 1.19 ?W/MHz power index, 2 ps p-p jitter, and 6 lock-in cycles. The minimal operation frequency is 200 MHz and 60 MHz when the input duty cycle is 50% and 85%, respectively.

A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop

In this paper, a fast-locking all-digital deskew buffer with duty cycle correction is proposed and implemented. A cyclic time-to-digital converter is introduced to decrease the locking time in conventional register-controlled delay-locked loop to only two input clock cycles in coarse tuning. With the aid of the three half delay lines technique, the mismatch between half delay lines causing the duty cycle distortion can be alleviated by interpolation. A balanced edge combiner to achieve a precise 50% output clock is also presented. A test chip is fabricated in 0.18-μm technology to demonstrate the feasibility of the proposed architecture. The circuit can accept the input clock rates from 250 to 625 MHz with the duty cycle variation within 30% and 70% to generate 50% output clocks. It preserves the capability of closed-loop control with a small area and power consumption.

A Fast-Locking All-Digital Deskew Buffer With Duty-Cycle Correction

A 1.5–3.3 GHz, 7 mW, all-digital delay-locked loop (ADDLL) designed in a UMC 130-nm CMOS technology is presented in this paper. The proposed ADDLL uses the modified successive approximation register to control a NAND-based coarse delay line, which enables wider operating frequency range and small intrinsic delay. The inverter-based fine delay line is controlled by an XOR-based up/down counter with dead-zone free phase detector to overcome the dead-zone problem of conventional phase detectors. The D-type flip-flops in the phase detector are modified to detect sub-ps level delay difference between the input and output clocks, so that a delay resolution of better than 1 ps is achieved in the proposed design. The combination of both coarse and fine locking processes gives outstanding performance in terms of residual phase difference and output jitter. The overall design occupies 0.0077 mm2 area. The experimental results show that the peak-to-peak and root mean square jitters are 12 and 1.629 ps at 3.3 GHz, respectively, while the input jitter is 2.6 ps peak-to-peak and 612 fs rms.

1.5–3.3 GHz, 0.0077 mm2, 7 mW All-Digital Delay-Locked Loop With Dead-Zone Free Phase Detector in $0.13~\mu \text{m}$ CMOS

A 3 MHz-to-1.8 GHz, 94 $\mu\hbox {W}$ -to-9.5 mW, all-digital delay-locked loop (ADDLL) using 65-nm CMOS technology is presented. In this paper, a cyclic half-delay-line architecture that uses the same type of delay lines for cyclic delay determination and coarse locking is proposed and used to achieve the design goals of small footprint and fast locking for a large operating frequency range. In addition, a new delay structure is developed for the cyclic delay units and coarse delay line. In addition to clock gating, which is used to reduce power consumption in the lock-in state regardless of the clock frequency, the automatic bypassing of the cyclic operation is developed and used to reduce power consumption during high-frequency operation. Through the use of proposed techniques, the active area is reduced to only 0.0153 mm $^{2}$ , and the operating frequency range is from 3 MHz to 1.8 GHz. The measurement results show that the proposed ADDLL achieves a peak-to-peak jitter of 3 ps with 9.5 mW power consumption when operated at 1.8 GHz.

A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture

The conventional SAR controller for DLL applications is shown in this paper to have the problem of dead lock. With this problem, the DLLs adopting the SAR controller are useless because they will go unlocked forever in face of supply voltage and temperature variations. An improved SAR controller is proposed to overcome this problem and then to rescue the DLLs.

An improved SAR controller for DLL applications

This paper presents the design of a 1.0 V 150-550 MHz 65 nm ADDLL using a novel coarse-fine architecture and differential circuit techniques. When running at 550 MHz, this nanometer ADDLL achieves a peak-to-peak jitter of only 5 ps with the shortest 4 locking cycles, while consumes only 0.67 muW/MHz, about 72% reduction compared to the existing most power efficient ADDLL.

A 0.67μW/MHz, 5ps jitter, 4 locking cycles, 65nm ADDLL

This paper presents the design of a 55nm 1.0V 1GHz open-loop de-skewing circuit for clock synchronization in a SoC. All-digital architecture and circuit design techniques are adopted and developed to achieve small jitter, low power, super fast locking, and input duty-cycle independence. Even running at 1 GHz, the proposed circuit wakes up from sleep with only one-cycle locking time. Measurement results show a peak-to-peak jitter of 4 ps and a static phase error of 5.46 ps at 1 GHz. To the best of our knowledge, this is the first GHz open-loop de-skewing circuit achieving sub-|TW/MHz active power. By power gating, 84% of leakage power is saved in the sleep mode.

Chun-Yuan Cheng

Papers

A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop

A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture

An improved SAR controller for DLL applications

A 0.67μW/MHz, 5ps jitter, 4 locking cycles, 65nm ADDLL

A 55nm 1GHz one-cycle-locking de-skewing circuit