Showing papers by "Cicero S. Vaucher published in 2001"

Circuit Design for RF Transceivers

Abstract: 1. RF Design: Concepts and Technology 1.1 RF Specifications 1.1.1 Gain 1.1.2 Noise 1.1.3 Non-Linearity 1.1.4 Sensitivity 1.2 RF Device technology 1.2.1 Characterization and Modeling, Modeling, Cut-off Frequency, Maximum Oscillation Frequency, Input Limited Frequency, Output Limited Frequency, Maximum Available Bandwidth 1.2.2 Technology Choice, Double Poly Devices, Silicon-on-Anything, Comparison, SiGe Bipolar Technology, RF CMOS (updated for newer processes) 1.3 Passives 1.3.1 Resistors 1.3.2 Capacitors (updated for different layouts) 1.3.3 Planar Monolithic Inductors (updated as relation to newer processes) References (updated) 2. Antennas, Interface and substrate 2.1 Antennas 2.2 Bond wires 2.3 Transmission Lines 2.3.1 General Theory 2.3.2 Impedance Matching using Transmission Lines 2.3.3 Microstrip Lines and coplanar Lines 2.4 Bond Pads and ESD Devices 2.4.1 Bond Pads 2.4.2 ESD Devices, ggNMOST ESD Device, pn and np-diode ESD Device (updated for newer processes and detailed scaling effects) 2.5 Substrate 2.5.1 Substrate bounces 2.5.2 Design Techniques to Reduce the substrate bounce References (updated) 3. Low Noise Amplifiers 3.1 Specifications 3.2 Bipolar LNA designs 3.2.1 DCS applications in SOA, Design of the LNA, Measurements 3.2.2 Broadband LNA (new) 3.3 CMOS LNA Design 3.3.1 Single Transistor LNA, Design Steps, Simulation and Measurements 3.3.2 Classical LNA Design, The Design, Measurement Results 3.3.3 Broadband LNA (new) 3.4 Evaluation References (updated) 4. Mixers 4.1 Specification 4.2 Bipolar Mixer Design 4.3 CMOS mixers 4.3.1 Active CMOS mixer 4.3.2 Passive CMOS mixer, 1/f-Noise in mixer transistors, 1/f-Noise due to IF amplifier, 1/f-noise due to Switched-Capacitor Behavior 4.3.3 Concluding remarks References (Updated) 5. Case study Receiver front-ends (new) 5.1 Bluetooth (new) 5.2 IEEE 802.11a Standard (new) 6. RF Power Amplifier 6.1 Specification 6.1.1 Efficiency 6.1.2 Generic Amplifier Classes 6.1.3 Heating 6.1.4 Linearity 6.1.5 Ruggedness 6.2 Bipolar PA design 6.3 CMOS PA Design 6.4 Linearization Principles 6.4.1 Predistortion Technique 6.4.2 Phase-Correcting feedback 6.4.3 Envelope Elimination and Restoration (EER) 6.4.4 Cartesian Feedback 6.5 Case study: Bluetooth PA (new) References (updated) Note: Oscillator chapter: errors removed and updated throughout, sub-section headings probably quite similar but to be defined 7. Oscillators 7.1 Introduction 7.2 Specifications 7.3 LC oscillator 7.4 Ring oscillators 7.5 Phase noise modelling and simulation (new) 7.6 Typical oscillator performance (new) 7.7 Oscillator case studies (new), Wide range oscillators for mobile applications, Oscillators for ultra low-power wireless links, 10GHz CMOS VCO for WLAN, 10GHz QuBIC VCO for Satellite References (updated) 8. Frequency Synthesizers 8.1 Introduction 8.2 Integer-N PLL Architecture 8.3 Tuning System Specifications 8.3.1 Tuning Range 8.3.2

Data clocked recovery circuit

Abstract: A data clock recovery circuit comprises a controllable quadrature clock oscillator operating at half the data rate of data input to said circuit, and a phase detector logic having detector inputs coupled to the data input and having a detector output coupled to a frequency control input of the quadrature clock oscillator. The data clock recovery circuit further comprises a parallel arrangement of sampling devices, in particular flip-flops each having a clock input which is coupled to the controllable quadrature clock oscillator, a data input for the data input to said circuit, and a data output coupled to the phase detector. Accurate control of the phase of recovered data is possible with the present circuit, which is easy to integrate on a limited chip area and in a low power consuming way.

Differential phase-locked-loop circuit

Abstract: A differential charge pump with integrated common-mode control circuitry (100) for a fully differential phase-locked loop is described, having two output lines (OUT+; OUT-) and comprising a charge pump section (103) and a common-mode feedback section (106). In the charge pump section (103), current generating means (111, 112, 113, 114) generate a first current signal having a first magnitude and a certain polarity on said first signal output (OUT+), and a second current signal having a second magnitude and opposite polarity on said second signal output (OUT-). The common-mode feedback section (106) senses the common-mode voltage level (VCM) of said first and second signal outputs (OUT+, OUT-), compares said common mode voltage (VCM) with a reference voltage (VSET), and generates a feedback signal influencing said current generating means (111, 112, 113, 114) of the charge pump section (103), for increasing/decreasing the first magnitude of the first current signal and simultaneously decreasing/increasing the second magnitude of the second current signal, in order to steer said common-mode voltage level (VCM) towards said reference voltage (VSET).

Analysis of Random Jitter in a Clock Multiplying DLL Architecture

Abstract: In this paper, a thorough analysis of the jitter behavior of a Delay Locked Loop (DLL) based clock multiplying architecture is presented. The noise sources that are included in the analysis are the noise of the delay elements, the reference jitter and the noise of the Phase Frequency Detector and Charge Pump combination. It is shown that the effect of all noise sources on the output timing jitter can be minimized by minimizing the loop gain of the DLL. This means that the loop is merely used to tune the delay of the Delay Line to a nominal value of exactly one reference input period; the loop is ineffective in filtering jitter. The analysis results are verified using high-level simulations, with good agreement.