https://www.dcsc.tudelft.nl/~bdeschutter/pub/rep/00_07.pdf

Brief Equivalence of hybrid dynamical models

An inductorless low-noise amplifier (LNA) with active balun is proposed for multi-standard radio applications between 100 MHz and 6 GHz. It exploits a combination of a common-gate (CGH) stage and an admittance-scaled common-source (CS) stage with replica biasing to maximize balanced operation, while simultaneously canceling the noise and distortion of the CG-stage. In this way, a noise figure (NF) close to or below 3 dB can be achieved, while good linearity is possible when the CS-stage is carefully optimized. We show that a CS-stage with deep submicron transistors can have high IIP2, because the nugsldr nuds cross-term in a two-dimensional Taylor approximation of the IDS(VGS, VDS) characteristic can cancel the traditionally dominant square-law term in the IDS(VGS) relation at practical gain values. Using standard 65 nm transistors at 1.2 V supply voltage, we realize a balun-LNA with 15 dB gain, NF +20 dBm, while simultaneously achieving an IIP3 > 0 dBm. The best performance of the balun is achieved between 300 MHz to 3.5 GHz with gain and phase errors below 0.3 dB and plusmn2 degrees. The total power consumption is 21 mW, while the active area is only 0.01 mm2.

/pdf/wideband-balun-lna-with-simultaneous-output-balancing-noise-1hf6dchypp.pdf

Wideband Balun-LNA With Simultaneous Output Balancing, Noise-Canceling and Distortion-Canceling

This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixed-signal ICs and emerging systems-on-a-chip (SoC) designs. But due to the increasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuous-valued external world, there is a growing need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits. This paper describes the motivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, symbolic analysis, synthesis and optimization, layout generation, yield analysis and design centering, and test. This paper summarizes the problems for which viable solutions are emerging and those which are still unsolved.

/pdf/computer-aided-design-of-analog-and-mixed-signal-integrated-23xbvj9rc2.pdf

Computer-aided design of analog and mixed-signal integrated circuits

This thesis treats analysis and design of piecewise linear control systems. Piecewise linear systems capture many of the most common nonlinearities in engineering systems, and they can also be used for approximation of other nonlinear systems. Several aspects of linear systems with quadratic constraints are generalized to piecewise linear systems with piecewise quadratic constraints. It is shown how uncertainty models for linear systems can be extended to piecewise linear systems, and how these extensions give insight into the classical trade-offs between fidelity and complexity of a model. Stability of piecewise linear systems is investigated using piecewise quadratic Lyapunov functions. Piecewise quadratic Lyapunov functions are much more powerful than the commonly used quadratic Lyapunov functions. It is shown how piecewise quadratic Lyapunov functions can be computed via convex optimization in terms of linear matrix inequalities. The computations are based on a compact parameterization of continuous piecewise quadratic functions and conditional analysis using the S-procedure. A unifying framework for computation of a variety of Lyapunov functions via convex optimization is established based on this parameterization. Systems with attractive sliding modes and systems with bounded regions of attraction are also treated. Dissipativity analysis and optimal control problems with piecewise quadratic cost functions are solved via convex optimization. The basic results are extended to fuzzy systems, hybrid systems and smooth nonlinear systems. It is shown how Lyapunov functions with a discontinuous dependence on the discrete state can be computed via convex optimization. An automated procedure for increasing the flexibility of the Lyapunov function candidate is suggested based on linear programming duality. A Matlab toolbox that implements several of the results derived in the thesis is presented.

/pdf/piecewise-linear-control-systems-30b5ueuoym.pdf

Piecewise Linear Control Systems

We describe a new method for determining component values and transistor dimensions for CMOS operational amplifiers (op-amps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result, the amplifier design problem can be expressed as a special form of optimization problem called geometric programming, for which very efficient global optimization methods have been developed. As a consequence we can efficiently determine globally optimal amplifier designs or globally optimal tradeoffs among competing performance measures such as power, open-loop gain, and bandwidth. Our method, therefore, yields completely automated sizing of (globally) optimal CMOS amplifiers, directly from specifications. In this paper, we apply this method to a specific widely used operational amplifier architecture, showing in detail how to formulate the design problem as a geometric program. We compute globally optimal tradeoff curves relating performance measures such as power dissipation, unity-gain bandwidth, and open-loop gain. We show how the method can he used to size robust designs, i.e., designs guaranteed to meet the specifications for a variety of process conditions and parameters.

/pdf/optimal-design-of-a-cmos-op-amp-via-geometric-programming-4thsejbwi6.pdf

Optimal design of a CMOS op-amp via geometric programming

DARWIN is a tool that is able to synthesize CMOS opamps, on the basis of a genetic algorithm. A randomly generated initial set of opamps evolves to a set in which the topologies as well as the transistor sizes of the opamps are adapted to the required performance specifications. Several design examples illustrate the behavior of DARWIN.

/pdf/darwin-cmos-opamp-synthesis-by-means-of-a-genetic-algorithm-25o1s4a1hf.pdf

DARWIN: CMOS opamp Synthesis by Means of a Genetic Algorithm

From the Publisher:
Piecewise Linear Modeling and Analysis explains in detail all possible model descriptions to efficiently store piecewise linear functions starting with the Chua descriptions. Detailed explanation on how the model parameter can be obtained for a given mapping is provided and demonstrated by examples. The models are ranked to compare them and to show which model can handle the largest class of PL mappings. To analyse PL electrical networks a simulator is mandatory. Piecewise Linear Modeling and Analysis provides a detailed outline of a possible PL simulator, including pseudo-programming code. Several simulation domains like transcient, AC and distortion are discussed. The book explains the attractive features of PL simulators with respect to mixed-level and mixed-signal simulation while paying due regard also to hierarchical simulation. Piecewise Linear Modeling and Analysis shows in detail how many existing components in electrical networks can be modeled. These range from digital logic and analog basic elements such as transistors to complex systems like Phase-Locked Loops and detection systems. Simulation results are also provided. The book concludes with a discussion on how to find multiple solutions for PL functions or networks. Again, the most common techniques are outlined using clear examples. Piecewise Linear Modeling and Analysis is an indispensable guide for researchers and designers interested in network theory, network synthesis and network analysis.

Piecewise Linear Modeling and Analysis

This paper proposes to merge an I/Q current-commutating mixer with a noise-canceling balun-LNA. To realize a high bandwidth, the real part of the impedance of all RF nodes is kept low, and the voltage gain is not created at RF but in baseband where capacitive loading is no problem. Thus a high RF bandwidth is achieved without using inductors for bandwidth extension. By using an I/Q mixer with 25% duty-cycle LO waveform the output IF currents have also 25% duty-cycle, causing 2 times smaller DC-voltage drop after IF filtering. This allows for a 2 times increase in the impedance level of the IF filter, rendering more voltage gain for the same supply headroom. The implemented balun-LNA-I/Q-mixer topology achieves > 18 dB conversion gain, a flat noise figure < 5.5 dB from 500 MHz to 7 GHz, IIP2 = +20 dBm and IIP3 = -3 dBm. The core circuit consumes only 16 mW from a 1.2 V supply voltage and occupies less than 0.01 mm2 in 65 nm CMOS.

/pdf/the-blixer-a-wideband-balun-lna-i-q-mixer-topology-rbqtkd28r5.pdf

The Blixer , a Wideband Balun-LNA-I/Q-Mixer Topology

This paper describes a temperature sensor realized in a 65nm CMOS process with a batch-calibrated inaccuracy of ±0.5°C (3s) and a trimmed inaccuracy of ±0.2°C (3s) from −70°C to 125°C. This represents a 10-fold improvement in accuracy compared to other deep-submicron temperature sensors [1,2], and is comparable with that of state-of-the-art sensors implemented in larger-feature-size processes [3,4]. The sensor draws 8.3µA from a 1.2V supply and occupies an area of 0.1mm2, which is 45 times less than that of sensors with comparable accuracy [3,4]. These advances are enabled by the use of NPN transistors as sensing elements, the use of dynamic techniques i.e. correlated double sampling (CDS) and dynamic element matching (DEM), and a single room-temperature trim.

/pdf/a-1-2v-10uw-npn-based-temperature-sensor-in-65nm-cmos-with-2tj3m1cl0a.pdf

A 1.2V 10µW NPN-based temperature sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3s) from −70°C to 125°C

This paper describes a 2.4GHz Wake-up Receiver (WuRx) designed to operate with low-accuracy (≪0.5%) frequency references [1], enabling crystal-less and thus low-cost wireless sensor nodes (WSNs). Robustness to frequency error is achieved by combining non-coherent energy detection with a broadband-IF superheterodyne architecture, and by using a pulse-position-modulated (PPM) impulse radio (IR) modulation scheme [2]. The Rx front-end and the LO generator are duty-cycled at pulse level, thereby reducing the power consumption to less than 420µW, which is more than adequate for use in WSNs [2]. PPM-IR also enables the realization of an interferer-robust receiver without the use of bulky off-chip RF filters [3,4]. This 65nm CMOS fully integrated WuRx employs a duty-cycled LO generator and achieves a sensitivity of −82dBm at a data rate of 500kb/s with an energy efficiency of 830pJ/bit.

https://ris.utwente.nl/ws/files/5324247/Drago,_S._IEEE_ISSCC_2010.pdf

Domine M. W. Leenaerts

Papers

DARWIN: CMOS opamp Synthesis by Means of a Genetic Algorithm

Piecewise Linear Modeling and Analysis

The Blixer , a Wideband Balun-LNA-I/Q-Mixer Topology

A 1.2V 10µW NPN-based temperature sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3s) from −70°C to 125°C

A 2.4GHz 830pJ/bit duty-cycled wake-up receiver with −82dBm sensitivity for crystal-less wireless sensor nodes