Communication at millimeter wave (mmWave) frequencies is defining a new era of wireless communication. The mmWave band offers higher bandwidth communication channels versus those presently used in commercial wireless systems. The applications of mmWave are immense: wireless local and personal area networks in the unlicensed band, 5G cellular systems, not to mention vehicular area networks, ad hoc networks, and wearables. Signal processing is critical for enabling the next generation of mmWave communication. Due to the use of large antenna arrays at the transmitter and receiver, combined with radio frequency and mixed signal power constraints, new multiple-input multiple-output (MIMO) communication signal processing techniques are needed. Because of the wide bandwidths, low complexity transceiver algorithms become important. There are opportunities to exploit techniques like compressed sensing for channel estimation and beamforming. This article provides an overview of signal processing challenges in mmWave wireless systems, with an emphasis on those faced by using MIMO communication at higher carrier frequencies.

An Overview of Signal Processing Techniques for Millimeter Wave MIMO Systems

Hybrid analog/digital multiple-input multiple-output architectures were recently proposed as an alternative for fully digital-precoding in millimeter wave wireless communication systems. This is motivated by the possible reduction in the number of RF chains and analog-to-digital converters. In these architectures, the analog processing network is usually based on variable phase shifters. In this paper, we propose hybrid architectures based on switching networks to reduce the complexity and the power consumption of the structures based on phase shifters. We define a power consumption model and use it to evaluate the energy efficiency of both structures. To estimate the complete MIMO channel, we propose an open-loop compressive channel estimation technique that is independent of the hardware used in the analog processing stage. We analyze the performance of the new estimation algorithm for hybrid architectures based on phase shifters and switches. Using the estimate, we develop two algorithms for the design of the hybrid combiner based on switches and analyze the achieved spectral efficiency. Finally, we study the tradeoffs between power consumption, hardware complexity, and spectral efficiency for hybrid architectures based on phase shifting networks and switching networks. Numerical results show that architectures based on switches obtain equal or better channel estimation performance to that obtained using phase shifters, while reducing hardware complexity and power consumption. For equal power consumption, all the hybrid architectures provide similar spectral efficiencies.

Hybrid MIMO Architectures for Millimeter Wave Communications: Phase Shifters or Switches?

Hybrid analog/digital MIMO architectures were recently proposed as an alternative for fully-digitalprecoding in millimeter wave (mmWave) wireless communication systems. This is motivated by the possible reduction in the number of RF chains and analog-to-digital converters. In these architectures, the analog processing network is usually based on variable phase shifters. In this paper, we propose hybrid architectures based on switching networks to reduce the complexity and the power consumption of the structures based on phase shifters. We define a power consumption model and use it to evaluate the energy efficiency of both structures. To estimate the complete MIMO channel, we propose an open loop compressive channel estimation technique which is independent of the hardware used in the analog processing stage. We analyze the performance of the new estimation algorithm for hybrid architectures based on phase shifters and switches. Using the estimated, we develop two algorithms for the design of the hybrid combiner based on switches and analyze the achieved spectral efficiency. Finally, we study the trade-offs between power consumption, hardware complexity, and spectral efficiency for hybrid architectures based on phase shifting networks and switching networks. Numerical results show that architectures based on switches obtain equal or better channel estimation performance to that obtained using phase shifters, while reducing hardware complexity and power consumption. For equal power consumption, all the hybrid architectures provide similar spectral efficiencies.

A truly modular and power-scalable architecture for low-power programmable frequency dividers is presented. The architecture was used in the realization of a family of low-power fully programmable divider circuits, which consists of a 17-bit UHF divider, an 18-bit L-band divider, and a 12-bit reference divider. Key circuits of the architecture are 2/3 divider cells, which share the same logic and the same circuit implementation. The current consumption of each cell can be determined with a simple power optimization procedure. The implementation of the 2/3 divider cells is presented, the power optimization procedure is described, and the input amplifiers are briefly discussed. The circuits were processed in a standard 0.35 /spl mu/m bulk CMOS technology, and work with a nominal supply voltage of 2.2 V. The power efficiency of the UHF divider is 0.77 GHz/mW, and of the L-band divider, 0.57 GHz/mW. The measured input sensitivity is >10 mV rms for the UHF divider, and >20 mV rms for the L-band divider.

A family of low-power truly modular programmable dividers in standard 0.35-/spl mu/m CMOS technology

A fully-integrated FMCW radar system for automotive applications operating at 77 GHz has been proposed. Utilizing a fractional- synthesizer as the FMCW generator, the transmitter linearly modulates the carrier frequency across a range of 700 MHz. The receiver together with an external baseband processor detects the distance and relative speed by conducting an FFT-based algorithm. Millimeter-wave PA and LNA are incorporated on chip, providing sufficient gain, bandwidth, and sensitivity. Fabricated in 65-nm CMOS technology, this prototype provides a maximum detectable distance of 106 meters for a mid-size car while consuming 243 mW from a 1.2-V supply.

A Fully-Integrated 77-GHz FMCW Radar Transceiver in 65-nm CMOS Technology

A receiver architecture with inaudible quality checks is suitable for global applications. The receiver has few external components and requires no mechanical alignment. A simplified block diagram of the new in-car entertainment IC is shown. The AM section is a double-conversion receiver.

http://ieeexplore.ieee.org/iel4/5508/14797/00672403.pdf

A global car radio IC with inaudible signal quality checks

We identify limitations of the models for phase noise in frequency dividers by Egan and by Phillips and present a new model applicable to both high frequency and low power frequency divider design. Further, we design both synchronous and asynchronous frequency divider test chips that allow us to observe experimentally the effects of noise accumulation, sampling frequency and biasing conditions on the total phase noise performance of frequency dividers. We use our measurements to validate the simulated values obtained by time domain phase noise analysis offered by the commercial simulator Spectre RF. The measured data show good agreement with the simulation results.

/pdf/phase-noise-in-frequency-divider-circuits-1elzet360k.pdf

Phase noise in frequency divider circuits

This paper presents an 8-elements phased array receiver front-end in 45nm CMOS technology. The receiver uses a 4-bit resolution RF phase shifter to compensate for the free-space propagation delay and an active eight-to-one power combiner enabling beam-forming. Each path shows more than 15.8dB of power gain with &#60;0.5 dB of RMS gain variation for all 16 phase settings over the 3-dB gain bandwidth from 53.2GHz – 64.6GHz. The measured RMS phase error is &#60;5° over the same band, achieving greater than 4-bit accuracy. Within the 3-dB gain bandwidth, the single-path NF ranges from 4.3dB to 6.3dB. The total power consumption is 613mW and the overall chip size is 4.8×1.5mm2

A 60GHz wideband low noise eight-element phased array RX front-end for beam steering communication applications in 45nm CMOS

A low-power fully integrated synthesizer for Bluetooth applications is presented. The circuit with quadrature output and 15 mW power dissipation has been designed in a 0.18 µm CMOS process with 1.8 V supply voltage. The only external component is a 64 MHz X-tal. Measurements have been performed on packaged samples mounted on a FR-4 board and show that the B luetooth requirements are met. The measured phase noise is below -120dBc/Hz at 3 MHz offset and the resulting residual FM is 4.5 kHz.

http://ieeexplore.ieee.org/iel5/9921/31530/01471474.pdf

A 15mW fully integrated I/Q synthesizer for bluetooth in 0.18&#181;m CMOS

In an electronic circuit for forming an antenna pattern the antenna signals having the required phase shift are generated by means of two phase locked loops which have a common reference signal. A control current which is added at the output node of the charge pump (26) and/or (27) is used to control the phase shift of the antenna signals. This allows the implementation of the phase shift operation in the analogue domain, which decreases the cost of a corresponding consumer device, such as a car-radio or a mobile communication system.

Cicero S. Vaucher

Papers

A global car radio IC with inaudible signal quality checks

Phase noise in frequency divider circuits

A 60GHz wideband low noise eight-element phased array RX front-end for beam steering communication applications in 45nm CMOS

A 15mW fully integrated I/Q synthesizer for bluetooth in 0.18µm CMOS

A method and system for forming an antenna pattern

Cicero S. Vaucher

Papers

A global car radio IC with inaudible signal quality checks

Phase noise in frequency divider circuits

A 60GHz wideband low noise eight-element phased array RX front-end for beam steering communication applications in 45nm CMOS

A 15mW fully integrated I/Q synthesizer for bluetooth in 0.18&#181;m CMOS

A method and system for forming an antenna pattern

A 15mW fully integrated I/Q synthesizer for bluetooth in 0.18µm CMOS