This paper describes a 160 MHz 500 mW 32 b StrongARM(R) microprocessor designed for low-power, low-cost applications. The chip implements the ARM(R) V4 instruction set and is bus compatible with earlier implementations. The pin interface runs at 3.3 V but the internal power supplies can vary from 1.5 to 2.2 V, providing various options to balance performance and power dissipation. At 160 MHz internal clock speed with a nominal Vdd of 1.65 V, it delivers 185 Dhrystone 2.1 MIPS while dissipating less than 450 mW. The range of operating points runs from 100 MHz at 1.65 V dissipating less than 300 mW to 200 MHz at 2.0 V for less than 900 mW. An on-chip PLL provides the internal clock based on a 3.68 MHz clock input. The chip contains 2.5 million transistors, 90% of which are in the two 16 kB caches. It is fabricated in a 0.35-/spl mu/m three-metal CMOS process with 0.35 V thresholds and 0.25 /spl mu/m effective channel lengths. The chip measures 7.8 mm/spl times/6.4 mm and is packaged in a 144-pin plastic thin quad flat pack (TQFP) package.

A 160 MHz 32 b 0.5 W CMOS RISC microprocessor

This paper investigates the effect of lowering the supply and threshold voltages on the energy efficiency of CMOS circuits. Using a first-order model of the energy and delay of a CMOS circuit, we show that lowering the supply and threshold voltage is generally advantageous, especially when the transistors are velocity saturated and the nodes have a high activity factor, In fact, for modern submicron technologies, this simple analysis suggests optimal energy efficiency at supply voltages under 0.5 V. Other process and circuit parameters have almost no effect on this optimal operating point. If there is some uncertainty in the value of the threshold or supply voltage, however, the power advantage of this very low voltage operation diminishes. Therefore, unless active feedback is used to control the uncertainty, in the future the supply and threshold voltage will not decrease drastically, but rather will continue to scale down to maintain constant electric fields.

/pdf/supply-and-threshold-voltage-scaling-for-low-power-cmos-2zwloxdyu4.pdf

Supply and threshold voltage scaling for low power CMOS

A system is proposed to convert ambient mechanical vibration into electrical energy for use in powering autonomous low-power electronic systems. The energy is transduced through the use of a variable capacitor, which has been designed with MEMS (microelectromechanical systems) technology. A low-power controller IC has been fabricated in a 0.6 /spl mu/m CMOS process and has been tested and measured for losses. Based on the tests, the system is expected to produce 8 /spl mu/W of usable power.

/pdf/vibration-to-electric-energy-conversion-3azjp1ac07.pdf

Vibration-to-electric energy conversion

Practical considerations in the design of CMOS charge pumps are discussed. The non-ideal effects of the charge pump due to the leakage current, the mismatch, and the delay offset in the P/FD are quantitatively analyzed. To use the appropriate charge pump in various PLL applications, several architectures are investigated and their performances are compared. The improved design of both the single-ended and the differential charge pumps are presented with the simulation result.

Design of high-performance CMOS charge pumps in phase-locked loops

A digital delay-locked loop (DLL) that achieves infinite phase range and 40-ps worst case phase resolution at 400 MHz was developed in a 3.3-V, 0.4-/spl mu/m standard CMOS process. The DLL uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correcting multiplexers. This more easily process portable DLL achieves jitter performance comparable to a more complex analog DLL when placed into identical high-speed interface circuits fabricated on the same test-chip die. At 400 MHz, the digital DLL provides <250 ps peak-to-peak long-term jitter at 3.3 V and operates down to 1.7 V, where it dissipates 60 mW. The DLL occupies 0.96 mm/sup 2/.

A portable digital DLL for high-speed CMOS interface circuits

This paper describes a low-power microprocessor clock generator based upon a phase-locked loop (PLL). This PLL is fully integrated onto a 2.2-million transistors microprocessor in a 0.35-/spl mu/m triple-metal CMOS process without the need for external components. It operates from a supply voltage down to 1 V at a VCO frequency of 320 MHz. The PLL power consumption is lower than 1.2 mW at 1.35 V for the same frequency. The maximum measured cycle-to-cycle jitter is /spl plusmn/150 ps with a square wave superposed to the supply voltage with a peak-to-peak amplitude of 200 mV and rise/fall time of about 30 ps. The input frequency is 3.68 MHz and the PLL internal frequency ranges from 176 MHz up to 574 MHz, which correspond to a multiplication factor of about 100.

A 320 MHz, 1.5 mW@1.35 V CMOS PLL for microprocessor clock generation

https://ieeexplore.ieee.org/iel2/3508/10440/00488540.pdf

FA 8.2 A 320MHz, 1.5mW at 1.35V CMOS PLL for Microprocessor Clock Generation

This paper reports on the design of a phase-locked-loop (PLL) for on-chip clock generation for a high-performance microprocessor (/spl mu/P). The power consumption of the /spl mu/P has been reduced by scaling down the supply voltage. The whole system has been implemented using a 0.35/spl mu/m CMOS process that features low-threshold voltages for MOS devices to maintain the speed performance. The /spl mu/P can be set in idle mode to further reduce the overall power consumption. To allow fast recovery from the /spl mu/P idle mode, the PLL runs continuously during this mode. Therefore, the power consumption of the PLL has to be minimized. To obtain the highest performance from the /spl mu/P, the output jitter of the PLL has to be as low as possible. The power switching noise generated by the running /spl mu/P directly affects the output jitter of the on-chip PLL. In summary, the challenge was to design a PLL which combines limited jitter, low-supply voltage and low-power consumption.

A 320 MHz, 1.5 mW at 1.35 V CMOS PLL for microprocessor clock generation

A micro-power circuit is encapsulated with a 2.1 MHz ZT-cut quartz in a vacuum package. The oscillator core has 2 complementary active MOSFETS and amplitude stabilization. New coupling and biasing circuits, and dynamic frequency dividers allow to achieve ±2 ppm frequency stability down to 1.8 V with a current under 0.5 ?A.

A 2.1 MHz Crystal Oscillator Time Base with a Current Consumption under 500 nA

A micropower crystal oscillator module for watch applications is presented. The integrated circuit is encapsulated with a 2.1-MHz crystal in a miniature vacuum package to reduce parasitic effects. The circuit comprises frequency tuning with a resolution of /spl plusmn/3 s/year ~/spl plusmn/0.1 parts per million (ppm)\ and auxiliary circuits. A single output delivers a signal of 16 384 Hz with a frequency stability of /spl plusmn/2 ppm over the temperature range (-10 to 70/spl deg/C). The oscillator core has two complementary active MOSFET's and amplitude stabilization in order to get both low power consumption and high stability. New coupling and biasing circuits between the oscillator and the dynamic frequency dividers allow to achieve a current consumption under 0.5 /spl mu/A for a supply voltage between 1.8 and 3.5 V.

D. Aebischer

Papers

A 320 MHz, 1.5 mW@1.35 V CMOS PLL for microprocessor clock generation

FA 8.2 A 320MHz, 1.5mW at 1.35V CMOS PLL for Microprocessor Clock Generation

A 320 MHz, 1.5 mW at 1.35 V CMOS PLL for microprocessor clock generation

A 2.1 MHz Crystal Oscillator Time Base with a Current Consumption under 500 nA

A 2.1-MHz crystal oscillator time base with a current consumption under 500 nA