This paper gives an overview on some state-of-the-art characterization methods of SiO2/4H-SiC interfaces in metal oxide semiconductor field effect transistors (MOSFETs). In particular, the work compares the benefits and drawbacks of different techniques to assess the physical parameters describing the electronic properties and the current transport at the SiO2/SiC interfaces (interface states, channel mobility, trapping phenomena, etc.). First, the most common electrical characterization techniques of SiO2/SiC interfaces are presented (e.g., capacitance- and current-voltage techniques, transient capacitance, and current measurements). Then, examples of electrical characterizations at the nanoscale (by scanning probe microscopy techniques) are given, to get insights on the homogeneity of the SiO2/SiC interface and the local interfacial doping effects occurring upon annealing. The trapping effects occurring in SiO2/4H-SiC MOS systems are elucidated using advanced capacitance and current measurements as a function of time. In particular, these measurements give information on the density (~1011 cm−2) of near interface oxide traps (NIOTs) present inside the SiO2 layer and their position with respect to the interface with SiC (at about 1–2 nm). Finally, it will be shown that a comparison of the electrical data with advanced structural and chemical characterization methods makes it possible to ascribe the NIOTs to the presence of a sub-stoichiometric SiOx layer at the interface.

https://www.mdpi.com/1996-1073/12/12/2310/pdf

Characterization of SiO2/4H-SiC Interfaces in 4H-SiC MOSFETs: A Review

It is shown that the charge pumping (CP) technique can be used for extraction of the depth concentration profile of traps situated in the oxide of metal-oxide-semiconductor (MOS) transistors, near and at the Si-SiO/sub 2/ interface. The trap density is obtained from the variation of the charge pumping current as a function of frequency, the other measurement parameters being kept constant. The concentration profiles are measured on n and p-channel transistors from several technologies, and on virgin and stressed devices. The results show that the trap concentration decreases rapidly from the Si-SiO/sub 2/ interface in the direction of the oxide depth and suggest that it becomes constant at a fraction of a nanometer from the silicon interface. The method easily demonstrates the trap creation due to Fowler-Nordheim stress. The profiles compare favorably with those measured using a new drain-current transient technique. In all cases, the integration of the depth concentration profiles leads to the interface trap densities measured using the conventional charge pumping method.

In-depth exploration of Si-SiO/sub 2/ interface traps in MOS transistors using the charge pumping technique

An analysis methodology for charge pumping (CP) measurements was developed and applied to extract spatial distributions of traps in SiO 2/HfO2 gate stacks. This analysis indicates that the traps accessible by CP measurements in the frequency range down to a few kilohertz are located primarily within the SiO2 layer and HfO2/SiO2 interface region. The trap density in the SiO2 layer increases closer to the high-kappa dielectric, while the trap spatial profile as a function of the distance from the high-kappa film was found to be dependent on high-kappa film characteristics. These results point to interactions with the high-kappa dielectric as a cause of trap generation in the interfacial SiO2 layer

Spatial Distributions of Trapping Centers in $ \hbox{HfO}_{2}/\hbox{SiO}_{2}$ Gate Stack

A detailed examination of hot-carrier-induced degradation in MOSFETs from a 0.25-/spl mu/m and a 0.1-/spl mu/m technology is performed. Although the worst case stress condition depends on the stress voltage, channel length, and oxide thickness, I/sub b,peak/ is projected to be the worst case stress condition at the operating voltage for both nMOSFETs and pMOSFETs. Post-metallization anneal (PMA) in deuterium can significantly improve the device lifetime if the primary degradation mechanism at the stress condition is interface trap generation due to interface depassivation by energetic electrons.

Projecting lifetime of deep submicron MOSFETs

For pt. I see ibid., vol. 49, pp. 247-53 (2002).The assessment of the physical mechanisms governing the degradation of thin oxides is a very important and, unfortunately, elusive issue that has raised significant debate in recent literature. In this paper, we first use some of the results reported in Pt. I to estimate a reasonable boundary for the efficiency of a possible hydrogen release (HR) mechanism and argue that the HR appears too weak to explain our measurements of stress-induced leakage current (SILC) produced by Fowler-Nordheim (FN) tunneling stress measurements. Then, we present an in-depth investigation of the anode hole injection (AHI) mechanism at low stress gate voltages (V/sub G/). To this purpose, we used both previously discussed and ad hoc devised characterization techniques. Our results indicate that AHI is still operative at V/sub G/ lower than previously experimentally demonstrated. Furthermore, the correlation between the energy of holes at the anode, their injection into the oxide, and the eventual generation of SILC strongly indicate that AHI is the mechanism governing oxide degradation in the considered stress conditions.

On interface and oxide degradation in VLSI MOSFETs. II. Fowler-Nordheim stress regime

An analytical expression of the charge pumping (CP) current in a MOS device is derived for fast and slow interface traps, after assuming short gate bias transition times and neglecting the emission of carriers In the case of fast interface traps, this simple CP formulation enables a good description of the charge pumping characteristics for general purpose CP configurations It is used to demonstrate the influence of the doping concentration on the CP characteristics It is also shown that the slow oxide traps induce a recombination current which can be of the same order of magnitude compared to that due to the fast interface traps The characteristics of this current are discussed in terms of the trap parameters In the case of a continuum of volume oxide traps, the apparent interface trap density, which is measured in the conventional CP technique, is also investigated and discussed for state-of-the-art MOS structures

Analytical study of the contribution of fast and slow oxide traps to the charge pumping current in MOS structures

Recently, the extraction of interface trap densities in MOSFET’s with ultrathin oxides, down to 1.2 nm, has been reported [MRS 2002 Spring meeting, San Francisco, April 1–5, MRS Proceedings 706, 2002, p. 293; IEEE Electron Dev. Lett. 23 (2002) 658]. The simplicity of the charge pumping (CP) method used contrasts with the heavy numerical calculations required to account for quantum mechanical effects in such structures due to oxide thickness and high doping concentrations. The reliability of the small gate pulse CP method proposed is discussed. The contribution of carrier emission, neglected in the model, is analyzed with regard to the experimental conditions used for the measurements and is shown to be negligible. Using a device with a thick oxide, the reliability of this approach is demonstrated by comparing the results with those obtained using the conventional large gate pulse CP mode. The effect, on the results, of quantization of the inversion and accumulation layers and of the polysilicon dark space is also addressed. Both have a negligible impact on the trap densities obtained. It is also shown that the trap cross sections can be extracted from the same measurements. Devices with oxides from 2.3 to 1.2 nm thick are studied. The interface trap densities and the trap cross sections are found independent of the oxide thickness.

Electrical properties of Si–SiO2 interface traps and evolution with oxide thickness in MOSFET’s with oxides from 2.3 to 1.2 nm thick

A compact analytical model for charge pumping (CP) is derived. It accounts for emission during the high and low gate bias levels and assumes instantaneous transition edges. This model, which does not apply on the top of the CP curves when using large gate voltage swings, where emission fully proceeds during the transitions edges of the gate signal, applies on all the other regions provided that the transition times of the gate signal are much shorter than the times at steady state biases. Therefore it holds at large bias swings on both edges of Elliot curves and at small bias swings on the whole Elliot curves provided that the interface traps are completely filled [1] . It is compared with the analytical model proposed by Wachnik and Lowney [2] in which emission is not accounted for at all. This model, which holds at Elliot curve maxima when small voltage swings are used, has been shown to be extremely useful for studying interface trap properties [1] , [2] , [3] , [4] . The CP model proposed primarily, that of Brugler and Jespers [5] , is used as a reference. The model derived in this article very satisfactorily fits the experimental curves in the regions of large CP current where it holds. Discrepancies at low current levels are due to the well-known contribution of the transistor source and drain regions or could be due to edge effects. Comparing the different models and the experimental curves allows to evaluate emission and capture during different regions of the gate bias period. The three regions of CP response, depending on the gate voltage swing and involving or not emission and the full filling of the interface traps, are also evidenced.

D. Bauza

Papers

Analytical study of the contribution of fast and slow oxide traps to the charge pumping current in MOS structures

Electrical properties of Si–SiO2 interface traps and evolution with oxide thickness in MOSFET’s with oxides from 2.3 to 1.2 nm thick

An analytical model for charge pumping below strong inversion and accumulation