A general scheduling methodology is presented that can be integrated into specialized or general-purpose high-level synthesis systems. An initial version of the force-directed scheduling algorithm at the heart of this methodology was originally presented by the authors in 1987. The latest implementation of the logarithm introduced here reduces the number of functional units, storage units, and buses required by balancing the concurrency of operations assigned to them. The algorithm supports a comprehensive set of constraint types and scheduling modes. These include multicycle and chained operations; mutually exclusive operations; scheduling under fixed global timing constraints with minimization of functional unit costs, minimization of register costs, and minimization of global interconnect requirements; scheduling with local time constraints (on operation pairs); scheduling under fixed hardware resource constraints; functional pipelining; and structural pipeline (use of pipeline functional units). Examples from current literature, one of which was chosen as a benchmark for the 1988 High-Level Synthesis Workshop, are used to illustrate the effectiveness of the approach. >

Force-directed scheduling for the behavioral synthesis of ASICs

Ethnocentrism: Theories of conflict, ethnic attitudes, and group behavior.

This book provides an up-to-date account of RNSs and arithmetic. It covers the underlying mathematical concepts of RNSs; the conversion between conventional number systems and RNSs; the implementation of arithmetic operations; various related applications are also introduced. In addition, numerous detailed examples and analysis of different implementations are provided.

Residue Number Systems: Theory and Implementation

Horizontal architectures are attractive for cost-effective, high performance scientific computing. They are, however, very difficult to schedule. Consequently, it is difficult to develop compilers that can generate efficient code for such architectures. The polycyclic architecture has been developed specifically to make the task of scheduling easy. As a result, it has been possible to develop a powerful scheduling algorithm that yields optimal and near-optimal schedules for iterative computations. This novel architecture and this scheduling algorithm are the topic of this paper.

Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing

We present a survey of the state-of-the-art techniques used in performing data and memory-related optimizations in embedded systems. The optimizations are targeted directly or indirectly at the memory subsystem, and impact one or more out of three important cost metrics: area, performance, and power dissipation of the resulting implementation.We first examine architecture-independent optimizations in the form of code transoformations. We next cover a broad spectrum of optimization techniques that address memory architectures at varying levels of granularity, ranging from register files to on-chip memory, data caches, and dynamic memory (DRAM). We end with memory addressing related issues.

Data and memory optimization techniques for embedded systems

An algorithm to synthesize registers using multiport memories during data-path synthesis is presented. The proposed approach considers not only the access requirements of registers but also their interconnection to operators in order to minimize required interconnections. The same approach can be applied to select the optimum number of buses in a multibus architecture. The method is illustrated with an example. >

Allocation of multiport memories in data path synthesis

The problem of minimizing the bit dimension of control memories in microprogrammed digital computers is considered in this paper. We start essentially with the same basic formulation as that of Grasselli and Montanari [2]. However, in order to minimize the computational requirements, we start directly with the set of maximum compatibility classes of microcommands whose number is usually small, and readily obtain near-minimal irredundant solutions. A minimal solution is then obtained from the irredundant solutions.

On Control Memory Minimization in Microprogrammed Digital Computers

Special-purpose instruction set processors (ISPs) challenge compilers because of instruction level parallelism, small numbers of registers, and highly specialized register capabilities. Many traditionally separate subproblems in code generation have been unified and jointly optimized within a single integer linear programming (ILP) model. ILP modeling provides a powerful methodology for generating high-quality code for a variety of ISPs. >

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An integrated approach to retargetable code generation

This paper is concerned with the sign detection problem in residue number systems. The proposed solution is applicable only to nonredundant systems. It is shown that under rather general conditions an explicit, closed formula for the sign function can be obtained. In a special case, when one of the moduli is 2, the sign function becomes an EXCLUSIVE-OR function. A sign detection algorithm is proposed and methods of implementing the algorithm are presented.

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Sign Detection in Residue Number Systems

This correspondence describes an implementation scheme for the operations of addition and subtraction in the residue number systems. The method is based on the property that the set of residues modulo m form a finite group under addition and subtraction (modulo m). The proposed adder/subtractor structure is very systematic and, hence, suitable for MSI/LSI realization.

D.K. Banerji

Papers

Allocation of multiport memories in data path synthesis

On Control Memory Minimization in Microprogrammed Digital Computers

An integrated approach to retargetable code generation

Sign Detection in Residue Number Systems

A Novel Implementation Method for Addition and Subtraction in Residue Number Systems