D
D. K. Nayak
Researcher at University of Tokyo
Publications - 24
Citations - 444
D. K. Nayak is an academic researcher from University of Tokyo. The author has contributed to research in topics: Quantum well & Photoluminescence. The author has an hindex of 9, co-authored 23 publications receiving 440 citations. Previous affiliations of D. K. Nayak include Advanced Micro Devices & University of California, Los Angeles.
Papers
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Journal ArticleDOI
High-mobility p-channel metal-oxide-semiconductor field-effect transistor on strained Si
TL;DR: In this article, an enhancement mode p-channel metal-oxide-semiconductor field effect transistor (PMOSFET) is fabricated on a strained Si layer for the first time, where a biaxial strain in a thin Si layer is produced by pseudomorphically growing this layer on a Ge0.25Si0.75 buffer layer which is grown on a Si substrate.
Journal ArticleDOI
Low‐field hole mobility of strained Si on (100) Si1−xGex substrate
D. K. Nayak,Sang Kook Chun +1 more
TL;DR: Strain Hamiltonian and k⋅p theory are employed to calculate low-field hole mobility of strained Si layers on (100)Si1−xGex substrate as discussed by the authors.
Journal ArticleDOI
Enhancement of radiative recombination in Si‐based quantum wells with neighboring confinement structure
TL;DR: In this paper, a new class of Si-based quantum well structures (QWs), called neighboring confinement structure (NCS), was observed, which consists of a single pair of tensile−strained−Si layer and a compressivestrained Si layer sandwiched by completely relaxed Si1−xGex layer.
Journal ArticleDOI
Band-edge photoluminescence of SiGe/strained-Si/SiGe type-II quantum wells on Si(100)
TL;DR: In this article, a pseudomorphic Si layer is grown on this relaxed SiGe buffer to form SiGe/strained-Si/SiGe type-II (staggered) quantum wells.
Journal ArticleDOI
High-Mobility p-Channel Metal-Oxide-Semiconductor Field-Effect-Transistor on Strained Si
TL;DR: In this paper, an enhancement-mode high-mobility p-channel metal-oxide-semiconductor field effect transistor (MOSFET) is fabricated on a biaxially strained thin Si layer.