In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input.

Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization

Competitive learning is a general technique for training clustering and classification networks. We have developed an 11-transistor silicon circuit, that we term an automaximizing bump circuit, that uses silicon physics to naturally implement a similarity computation, local adaptation, simultaneous adaptation and computation and nonvolatile storage. This circuit is an ideal building block for constructing competitive-learning networks. We illustrate the adaptive nature of the automaximizing bump in two ways. First, we demonstrate a silicon competitive-learning circuit that clusters one-dimensional (1-D) data. We then illustrate a general architecture based on the automaximizing bump circuit; we show the effectiveness of this architecture, via software simulation, on a general clustering task. We corroborate our analysis with experimental data from circuits fabricated in a 0.35-/spl mu/m CMOS process.

/pdf/competitive-learning-with-floating-gate-circuits-2qonrjlis7.pdf

Competitive learning with floating-gate circuits

The Self-Organizing Map (SOM) algorithm has attracted an ever increasing amount of interest among researches and practitioners in a wide variety of elds The SOM and a variant of it, the LVQ, have been analyzed extensively, a number of variants of them have been developed and, perhaps most notably, they have been applied extensively within elds ranging from engineering sciences to medicine, biology, and economics We have collected a comprehensive list of 3343 scienti c papers that use the algorithms, have bene ted from them, or contain analyses of them The list is intended to serve as a source for literature surveys We have provided both a thematic and a keyword index to help nding articles of interest

Bibliography of Self-Organizing Map (SOM) Papers: 1981-1997

neural and fuzzy logic control of drives and power systems neural and fuzzy logic control of drives and power systems neural and fuzzy logic control of drives and power systems neural and fuzzy logic control of drives and power systems neural and fuzzy logic control of drives power systems neural and fuzzy logic control of drives and power systems neural and fuzzy logic control of drives and power systems chapter 8 fuzzy logic and neural network applications in fuzzy logic applications to power electronics and drives expert system, fuzzy logic, and neural network speed control of dc motor using fuzzy logic technique dynamic fuzzy-neural network controller for induction neural and fuzzy logic control of drives and power systems advanced fuzzy systems design and applications khbd adaptive neural fuzzy inference systems controller for induction motor drive using fuzzy logic citeseerx embedded fuzzy controller for industrial applications direct torque control of induction motor using fuzzy logic application of learning methodologies in control of power fuzzy logic application for intelligent control of a speed control of dc motor using fuzzy pid controller application of fuzzy logic in engineering problems lnai 3949 dsp based fuzzy-neural speed tracking control a servo motor drives based on hybrid genetic algorithm gvpce(a ) m.tech. power electronics & drives 2013 neural fuzzy rule – based model reference adaptive control for artificial neural network and logic control for hvdc systems fuzzy logic control of maximum power point tracking for controlling speed of dc motor with fuzzy controller in speed control of brushless dc motor using fuzzy ijdacr design and performance evaluation of a fuzzy-logic-based maximum power point tracking of pv system using anfis power electronics and motor drives elsevier

/pdf/neural-and-fuzzy-logic-control-of-drives-and-power-systems-2gnm35onla.pdf

Neural and Fuzzy Logic Control of Drives and Power Systems

Analog VLSI signal processing is most effective when precision is not required, and is therefore an ideal solution for the implementation of perception systems. The possibility to choose the physical variable that represents each signal allows all the features of the transistor to be exploited opportunistically to implement very dense time- and amplitude-continuous processing cells. This paper describes a simple model that captures all the essential features of the transistor. This symmetrical model also supports the concept of pseudoconductance which facilitates the implementation of linear networks of transistors. Basic combinations of transistors in the current mirror, the differential pair, and the translinear loop are revisited as support material for the description of a variety of building blocks. These examples illustrate the rich catalogue of linear and nonlinear operators that are available for local and collective analog processing. The difficult problem of analog storage is addressed briefly, as well as various means for implementing the necessary intrachip and interchip communication.

/pdf/analog-vlsi-signal-processing-why-where-and-how-2l1fot2sfc.pdf

Analog VLSI signal processing: why, where, and how?

Kohonen maps are self-organizing neural networks that classify and quantify n-dimensional data into a one- or two-dimensional array of neurons. Most applications of Kohonen maps use simulations on conventional computers, eventually coupled to hardware accelerators or dedicated neural computers. The small number of different operations involved in the combined learning and classification process, however, makes the Kohonen model particularly suited to a dedicated VLSI implementation, taking full advantage of the parallelism and speed that can be obtained on the chip. A fully analog implementation of a one-dimensional Kohonen map, with on-chip learning and refreshment of on-chip analog synaptic weights, is proposed. The small number of transistors in each cell allows a high degree of parallelism in the operations, which greatly improves the computation speed compared to other implementations. The storage of analog synaptic weights, based on the principle of current copiers, is emphasized. It is shown that this technique can be used successfully for the realization of VLSI Kohonen maps. >

Analog implementation of a Kohonen map with on-chip learning

The purpose of the circuit presented was to test the implementation of dynamically refreshed analog memories using conventional CMOS technology with special care in achieving high resolution with small silicon area, and small read-write access time. The circuit prototype implements adjustable analog synaptic weights, compatible with an analog multiplier. The synaptic weights are dynamically refreshed with an on-chip system based on A/D and D/A conversion. The circuit has been fully tested, and a resolution of 7 bits per memory cell was measured. These are arranged in an array of 14*15 cells. A Kohonen neural network with on-chip learning system, which is based on this analog memory implementation is presented. The form of the `Mexican hat' and learning rate are digitally adjustable. No multipliers are required for this implementation, only differences are calculated. This circuit is under design.

Analog storage of adjustable synaptic weights

The current copier cell [1] is a versatile building block increasingly used in many analogue CMOS circuits. However, charge injection, noise, Early effect and leakage current affect its accuracy. The Letter focuses on charge injection. A new model, derived from the work of Vittoz [2] and Sheu et al. [3], is presented to predict the actual partition of the injected charges. The results are compared with experimental measurements on a test circuit.

Charge Injection in Current Copier Cells

The Redundant Signed Digit (RSD) algorithm has been successfully applied to cyclic and pipeline analog to digital converters [1][2]. It is superior to the Convertional Restoring (CR) algorithm regarding cancellation of offset errors, speed and an additional bit. In this paper, we consider the advantages resulting from an implementation in a current-mode pipeline analog to digital converter.

http://ieeexplore.ieee.org/iel5/5467852/5467859/05468078.pdf

A 10 bits Pipeline Current Mode A/D Converter

This paper describes the architecture and the implementation of a systolic processor dedicated to motion estimation which is one of the most important task in early vision processing. The input image is scanned by a standard video camera with 256 grey levels. Motion computing is based on the optical flow determination. An algorithm to detect multi-motion is proposed and is implemented in real-time in a systolic array.

D. Macq

Papers

Analog implementation of a Kohonen map with on-chip learning

Analog storage of adjustable synaptic weights

Charge Injection in Current Copier Cells

A 10 bits Pipeline Current Mode A/D Converter

Systolic Array Architecture for Early Vision Processing