This article discusses the potential role of software-based self-testing in the microprocessor test and validation process, as well as its supplementary role in other classic functional- and structural-test methods. In addition, the article proposes a taxonomy for different SBST methodologies according to their test program development philosophy, and summarizes research approaches based on SBST techniques for optimizing other key aspects.

Microprocessor Software-Based Self-Testing

The increasing complexity and size of digital designs, in conjunction with the lack of a potent verification methodology that can effectively cope with this trend, continue to inspire engineers and academics in seeking ways to further automate design verification. In an effort to increase performance and to decrease engineering effort, research has turned to artificial intelligence (AI) techniques for effective solutions. The generation of tests for simulation-based verification can be guided by machine-learning techniques. In fact, recent advances demonstrate that embedding machine-learning (ML) techniques into a coverage-directed test generation (CDG) framework can effectively automate the test generation process, making it more effective and less error-prone. This article reviews some of the most promising approaches in this field, aiming to evaluate the approaches and to further stimulate more directed research in this area.

Coverage-Directed Test Generation Automated by Machine Learning -- A Review

Embedded microprocessor cache memories suffer from limited observability and controllability creating problems during in-system tests. This paper presents a procedure to transform traditional march tests into software-based self-test programs for set-associative cache memories with LRU replacement. Among all the different cache blocks in a microprocessor, testing instruction caches represents a major challenge due to limitations in two areas: 1) test patterns which must be composed of valid instruction opcodes and 2) test result observability: the results can only be observed through the results of executed instructions. For these reasons, the proposed methodology will concentrate on the implementation of test programs for instruction caches. The main contribution of this work lies in the possibility of applying state-of-the-art memory test algorithms to embedded cache memories without introducing any hardware or performance overheads and guaranteeing the detection of typical faults arising in nanometer CMOS technologies.

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Software-Based Self-Test of Set-Associative Cache Memories

Biased random instruction generators are commonly used in architectural verification of microprocessors, with biases specified manually by designers. As the complexity of processors grows, so does the complexity of specifying biases. Automatic bias generation speeds up the verification flow and may lead to better coverage of potential design errors. In this work, we present a genetic algorithm based framework to automatically generate biases. We target utilization of specific buffers for a new version of the PowerPC architecture. Our results show that the GA is effective in achieving high buffer utilization. Also, in targeting multiple objectives, the best approach to use depends on whether the objectives are related.

Automatic Bias Generation for Biased Random Instruction Generation

High power consumption during test may lead to yield loss and premature aging. In particular, excessive peak power during at-speed delay fault testing represents an important issue. In the literature, several techniques have been proposed to reduce peak power consumption during at-speed LOC or LOS delay testing. On the other hand, some experiments have proved that too much test power reduction might lead to test escape and reliability problems. So, in order to avoid any yield loss and test escape due to power issues during test, test power has to map the power consumed during functional mode. In literature, some techniques have been proposed to apply test vectors that mimic functional operation from the switching activity point of view. The process consists of shifting-in a test vector (at low speed) and then applying several successive at-speed clock cycles before capturing the test response. In this paper, we propose a novel flow to determine the functional power to be used as test power (upper and lower) limits during at-speed delay testing. This flow is also used for comparison purpose between the above-mentioned test scheme and power consumption during the functional operation mode of a given circuit. The proposed methodology has been validated on an Intel MC8051 micro controller synthesized in a 65nm industrial technology.

A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing

Testing communication peripherals in an environment of systems on a chip is particularly challenging. The authors explore two test program generation approaches-one fully automated and one deterministically guided-and propose a novel combination of the two schemes that can be applied in a generic manner on a wide set of communication cores.

Test Program Generation for Communication Peripherals in Processor-Based SoC Devices

Software-based self-test (SBST) is increasingly used for testing processor cores embedded in SoCs, mainly because it allows at-speed, low-cost testing, while requiring limited (if any) hardware modifications to the original design However, the method requires effective techniques for generating suitable test programs and for monitoring the results In the case of processor core testing, a particularly complex module to test is the cache controller, due to its limited accessibility and observability In this paper we propose a hybrid methodology that exploits an Infrastructure Intellectual Property (I-IP) to complement an SBST algorithm for testing the data and instruction cache controllers of embedded processors in SoCs In particular, the I-IP may be programmed to monitor the system buses and generate the appropriate feedback about the correct result of the executed programs (in terms of obtained hit or miss operations) The effectiveness of the proposed methodology is evaluated resorting to a sample SoC design

A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs

Testing SoC is a challenging task, especially when addressing complex and high- frequency devices. Among the different techniques that can be exploited, software-based selft-test (SBST) emerged as an effective solution, due some advantages it provides (no HW changes, at- speed testing, re-usability); however, the method requires effective techniques for generating suitable test programs. In this paper we face the issue of generating programs to test data caches (in particular their control part): a method is proposed, and some experimental results are provided to assess its effectiveness.

Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs

Caches are crucial components in modern processors (both stand-alone or integrated into SoCs) and their test is a challenging task, especially when addressing complex and high-frequency devices. While the test of the memory array within the cache is usually accomplished resorting to BIST circuitry implementing March test inspired solutions, testing the cache controller logic poses some specific issues, mainly stemming from its limited accessibility. One possible solution consists in letting the processor execute suitable test programs, allowing the detection of possible faults by looking at the results they produce. In this paper we face the issue of generating suitable programs for testing the replacement logic in set-associative caches that implement a deterministic replacement policy. A test program generation approach based on modeling the replacement mechanism as a Finite State Machine (FSM) is proposed. Experimental results with a cache implementing a LRU policy are provided to assess the effectiveness of the method.

On the Generation of Functional Test Programs for the Cache Replacement Logic

Software-based self-test strategies have been mainly proposed to tackle microprocessor testing issues, but may also be applied to peripheral testing However, testing highly embedded peripherals (eg, DMA or Interrupt controllers) is a challenging task, since their observability and controllability are even more reduced compared to microprocessors and to peripherals devoted to I/O communication (eg, serial or parallel ports) In this paper we describe an approach to develop functional tests for system peripherals embedded in SoCs that can be used for both design validation and testing The presented methodology requires two correlated phases: module configuration and module operation The first one prepares the peripheral on the different operation modes, whereas, the second one is in charge of exciting the whole device and observing its behavior A methodology for generating suitable test programs is proposed, and preliminary experimental results demonstrating the method effectiveness for an embedded DMA controller are finally reported

D. Ravotto

Papers

Test Program Generation for Communication Peripherals in Processor-Based SoC Devices

A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs

Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs

On the Generation of Functional Test Programs for the Cache Replacement Logic

A software-based self-test methodology for system peripherals