Showing papers by "David A. Johns published in 2002"

Variable-structure compensation of delta-sigma modulators: stability and performance

Abstract: Develops a compensation method for continuous-time delta-sigma modulators valid for loop filters of arbitrary order. The approach, based on variable-structure theory, accommodates multilevel quantization and dithering. Stability is rigorously proved under the assumption of infinite sampling rate and is accompanied by an analytic characterization of performance. A slight modification of the basic compensator provides a defence against parametric uncertainty through the use of variable-integrator damping.

Analog filter adaptation using a dithered linear search algorithm

Abstract: A variation of the differential steepest descent algorithm, here called the dithered linear search (DLS), is examined and applied to analog filter adaptation. The DLS algorithm is a gradient descent optimizer with a straightforward and robust hardware implementation. Gradient estimates are obtained by applying independent additive dither to all of the filter's parameters simultaneously and correlating the resulting changes in the output squared error to the dither signals. Unlike the popular LMS algorithm, the DLS algorithm does not require access to the filter's internal states. No additional analog hardware is required making it ideal for adaptive analog filters in mixed-signal systems. A theoretical analysis shows no gradient misalignment. The algorithm is verified on an integrated analog filter. The effects of dc offsets are also examined.

High-speed CMOS analog Viterbi detector for 4-PAM partial-response signaling

Abstract: In this paper, a 1-Gb/s analog Viterbi detector based on a 4-PAM duobinary scheme is discussed with experimental results for a 0.25-/spl mu/m CMOS implementation. This chip is the first analog integrated implementation of a reduced state sequence detector. Pipelining and parallel processing have been incorporated in this design for high-speed operation. Due to test equipment limitations, experimental results are given for 200-Mb/s operation while simulation results indicate a speed of 1 Gb/s. Power dissipation is 55 mW from a 2.5-V supply. The active area occupies 0.78 mm/sup 2/. Although a duobinary scheme has been the focus of this work for its application in optical links, this design can be readily modified or extended to other partial-response signaling schemes such as dicode and PR4.

Power efficient chip-to-chip signaling schemes

Abstract: In low voltage signaling for chip-to-chip digital communication, noise is a crucial factor and since common-mode noise is prevalent on matched printed circuit board (PCB) traces, differential signaling is an effective method for chip-to-chip communication. However, it needs two signal paths for transmitting one bit. Multi-level signaling can be used to reduce the number of required signal paths for transmitting one bit. To reduce the required signal power, this paper investigates several coding schemes for this application. A novel scheme, which improves the performance of ordinary 4-level pulse amplitude modulation (PAM) by roughly 3 dB, is proposed. Finally a low complexity method for an analog implementation of this scheme is presented.

A 5th order Gm-C filter in 0.25 /spl mu/m CMOS with digitally programmable poles and zeroes

Abstract: This paper describes a 5th order Gm-C filter in a 0.25 /spl mu/m CMOS technology. The signal path, including transconductors and Miller integrators, consists entirely of NMOS transistors for high speed operation. All poles and zeros are digitally programmable. A prototype configured for a lowpass response demonstrates a signal bandwidth of 45 MHz.

A CMOS 7–Gb/s power–efficient 4–PAM transmitter

Abstract: A novel power-efficient architecture for a multi-level PAM transmitter is proposed. A data look ahead technique is used to pre-switch the current sources so that drive current is reduced when transmitting small voltage levels. Interestingly, this transmitting small voltage need for a pre-driver block which also saves transmitter power. Based on this architecture, a 4-PAM transmitter is designed in 0.18µm standard digital CMOS technology. The transmitter achieves 3.5GS/s (7Gb/s) and occupies 0.16mm2. The output driver and the entire transmitter consumed only 11.25mW and 66mW, respectively.

Analogue adaptive filters

Abstract: In this chapter, to improve the reliability and cost of signal processing electronics, entire systems must be integrated on to a single chip. In many applications, an all-digital or all-analogue system is impossible because both analogue and digital external interfaces are required. So we must assume that both analogue and digital circuits will have to coexist on the same IC. The advance of digital process technologies will enable faster digital signal processing with a smaller integrated circuit area and lower power consumption. At the same time it will become increasingly difficult to implement accurate and linear analogue circuits. Therefore, analogue adaptive filters are likely to continue to be targeted at applications where they can simplify or reduce the analogue circuitry required elsewhere on the chip.