A forward-facing vision system for a vehicle includes a forward-facing camera disposed in a windshield electronics module attached at a windshield of the vehicle and viewing through the windshield. A control includes a processor that, responsive to processing of captured image data, detects taillights of leading vehicles during nighttime conditions and, responsive to processing of captured image data, detects lane markers on a road being traveled by the vehicle. The control, responsive to lane marker detection and a determination that the vehicle is drifting out of a traffic lane, may control a steering system of the vehicle to mitigate such drifting, with the steering system manually controllable by a driver of the vehicle irrespective of control by the control. The processor, based at least in part on detection of lane markers via processing of captured image data, determines curvature of the road being traveled by the vehicle.

Vision system for vehicle

The main characteristic of Reconfigurable Computing is the presence of hardware that can be reconfigured to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor. Reconfigurable computing systems join microprocessors and programmable hardware in order to take advantage of the combined strengths of hardware and software and have been used in applications ranging from embedded systems to high performance computing. Many of the fundamental theories have been identified and used by the Hardware/Software Co-Design research field. Although the same background ideas are shared in both areas, they have different goals and use different approaches.This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or "computing vehicles" to implement this powerful technology. It will take a reader with a background in the basics of digital design and software programming and provide them with the knowledge needed to be an effective designer or researcher in this rapidly evolving field.

· Treatment of FPGAs as computing vehicles rather than glue-logic or ASIC substitutes
· Views of FPGA programming beyond Verilog/VHDL
· Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

Reconfigurable computing is becoming increasingly attractive for many applications. This survey covers two aspects of reconfigurable computing: architectures and design methods. The paper includes recent advances in reconfigurable architectures, such as the Alters Stratix II and Xilinx Virtex 4 FPGA devices. The authors identify major trends in general-purpose and special-purpose design methods. It is shown that reconfigurable computing designs are capable of achieving up to 500 times speedup and 70% energy savings over microprocessor implementations for specific applications.

/pdf/reconfigurable-computing-architectures-and-design-methods-2g6ogsz88l.pdf

Reconfigurable computing: architectures and design methods

Image quality assessment (IQA) has been a topic of intense research over the last several decades. With each year comes an increasing number of new IQA algorithms, extensions of existing IQA algorithms, and applications of IQA to other disciplines. In this article, I first provide an up-to-date review of research in IQA, and then I highlight several open challenges in this field. The first half of this article provides discuss key properties of visual perception, image quality databases, existing full-reference, no-reference, and reduced-reference IQA algorithms. Yet, despite the remarkable progress that has been made in IQA, many fundamental challenges remain largely unsolved. The second half of this article highlights some of these challenges. I specifically discuss challenges related to lack of complete perceptual models for: natural images, compound and suprathreshold distortions, and multiple distortions, and the interactive effects of these distortions on the images. I also discuss challenges related to IQA of images containing nontraditional, and I discuss challenges related to the computational efficiency. The goal of this article is not only to help practitioners and researchers
keep abreast of the recent advances in IQA, but to also raise awareness of the key limitations of current IQA knowledge.

/pdf/seven-challenges-in-image-quality-assessment-past-present-4y53obboox.pdf

Seven Challenges in Image Quality Assessment: Past, Present, and Future Research

Steady advances in VLSI technology and design tools have extensively expanded the application domain of digital signal processing over the past decade. While application-specific integrated circuits (ASICs) and programmable digital signal processors (PDSPs) remain the implementation mechanisms of choice for many DSP applications, increasingly new system implementations based on reconfigurable computing are being considered. These flexible platforms, which offer the functional efficiency of hardware and the programmability of software, are quickly maturing as the logic capacity of programmable devices follows Moore's Law and advanced automated design techniques become available. As initial reconfigurable technologies have emerged, new academic and commercial efforts have been initiated to support power optimization, cost reduction, and enhanced run-time performance.

This paper presents a survey of academic research and commercial development in reconfigurable computing for DSP systems over the past fifteen years. This work is placed in the context of other available DSP implementation media including ASICs and PDSPs to fully document the range of design choices available to system engineers. It is shown that while contemporary reconfigurable computing can be applied to a variety of DSP applications including video, audio, speech, and control, much work remains to realize its full potential. While individual implementations of PDSP, ASIC, and reconfigurable resources each offer distinct advantages, it is likely that integrated combinations of these technologies will provide more complete solutions.

http://www.umiacs.umd.edu/~joseph/classes/enee640/fpga-dsp-survey.pdf

Reconfigurable Computing for Digital Signal Processing: A Survey

This paper presents a novel FPGA implementation of a two dimensional (8/spl times/8) point Discrete Cosine Transform. It is shown how the development of a suitable architectural style can produce high quality circuit designs for a specific technology, in this case the Xilinx XC6200 series of FPGA. Distributed arithmetic and exploitation of parallelism and pipelining are used to produce a DCT implementation on a single FPGA that operates at 25 frames per second with VGA resolution which is the equivalent of 2 million multiplications or additions per second.

Implementation of the 2D DCT using a Xilinx XC6264 FPGA

This implementation of a two-dimensional discrete cosine transform demonstrates the development of a suitable architectural style for a specific technology-in this case, the Xilinx XC6200 FPGA series. The design exploits distributed arithmetic, parallelism, and pipelining to achieve high-performance custom-computing implementation.

Applying an XC6200 to real-time image processing

In this paper, we present the IRIS architectural synthesis system for high-performance digital signal processing. This tool allows non-specialists to automatically derive VLSI circuit architectures from high-level, algorithmic representations, and provides a quick route to silicon implementation. By incorporating a novel synthesis methodology, called the Modular Design Procedure, within the IRIS system, parameterised models of complex and innovative DSP hardware can be derived and automatically assembled to create new DSP systems. The nature of this synthesis methodology is such that designers can explore a large range of architectural alternatives, whilst considering all the architectural implications of using specific hardware to realise the circuit. The applicability of IRIS is demonstrated using the design examples of a second order Infinite Impulse Response filter and a one-dimensional Discrete Cosine Transform circuit.

Architectural Synthesis of Digital Signal Processing Algorithms Using IRIS

This paper presents the design of a single chip adaptive beamformer which contains 5 million transistors and can perform 50 gigaflops. The core processor of the adaptive beamformer is a QR-array processor implemented on a fully efficient linear systolic architecture. The paper highlights a number of rapid design techniques that have been used to realise the design. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop the circuit layouts.

Rapid design of a single chip adaptive beamformer

This paper provides a review of technology that has emerged to facilitate pervasive brain-computer interface applications. Such technology is beginning to be applied to the human-computer interface, as part of multimodal interaction. As the technology taps into brain state and provides an associated quantitative assessment, it has potential for the real-time assessment of a person's cognitive state. As such, many emerging applications could be addressed such as the assessment of learning. In the future, it may even be possible to tune learning materials in a manner appropriate to the state of a user using a feedback loop. In particular, the interaction of brain-computer interface technology with technologies such as augmented reality holds some promise, however, the technology is as yet unverified beyond lifestyle and gaming interaction. Consequently, this paper aims to review low-cost, commercial brain-computer interface technologies and posits their use as an interaction modality within future learning environments.

David Trainor

Papers

Implementation of the 2D DCT using a Xilinx XC6264 FPGA

Applying an XC6200 to real-time image processing

Architectural Synthesis of Digital Signal Processing Algorithms Using IRIS

Rapid design of a single chip adaptive beamformer

The Potential of the Brain-Computer Interface for Learning: A Technology Review