Proceedings ArticleDOI
Implementation of the 2D DCT using a Xilinx XC6264 FPGA
David Trainor,J.-P. Heron,Roger Woods +2 more
- pp 541-550
TLDR
It is shown how the development of a suitable architectural style can produce high quality circuit designs for a specific technology, in this case the Xilinx XC6200 series of FPGA.Abstract:
This paper presents a novel FPGA implementation of a two dimensional (8/spl times/8) point Discrete Cosine Transform. It is shown how the development of a suitable architectural style can produce high quality circuit designs for a specific technology, in this case the Xilinx XC6200 series of FPGA. Distributed arithmetic and exploitation of parallelism and pipelining are used to produce a DCT implementation on a single FPGA that operates at 25 frames per second with VGA resolution which is the equivalent of 2 million multiplications or additions per second.read more
Citations
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Journal ArticleDOI
Seven Challenges in Image Quality Assessment: Past, Present, and Future Research
TL;DR: An up-to-date review of research in IQA is provided, and several open challenges in this field are highlighted, including key properties of visual perception, image quality databases, existing full-reference, no- reference, and reduced-reference IQA algorithms.
Patent
Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like)
Martin Vorbach,Robert Münch +1 more
TL;DR: In this paper, the first result data may be obtained using a plurality of configurable coarse-granular elements, and the first results may be subsequently processed using the plurality of configured granular elements.
Patent
Data processing device and method
Martin Vorbach,Alexander Thomas +1 more
TL;DR: In this paper, a data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses or communication lines operated at a second clock rate is described.
Patent
Data processing method and device
TL;DR: In this article, the first result data may be obtained using a plurality of configurable coarse-granular elements, and the first results may be subsequently processed using the plurality of configured granular elements.
Patent
Methods and devices for treating and processing data
Martin Vorbach,Volker Baumgarte +1 more
TL;DR: In this paper, a clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is precomputed at least in an additional cell.
References
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Proceedings ArticleDOI
Practical fast 1-D DCT algorithms with 11 multiplications
TL;DR: A class of practical fast algorithms is introduced for the discrete cosine transform (DCT) and the structure of many of the published algorithms can be found in members of this class.
Journal ArticleDOI
Fast algorithms for the discrete cosine transform
Ephraim Feig,S. Winograd +1 more
TL;DR: Algorithms for computing scaled DCTs and their inverses have applications in compression of continuous tone image data, where the DCT is generally followed by scaling and quantization.
Journal ArticleDOI
A Reconsideration of
TL;DR: FAULKNER as mentioned in this paper observed that the same expression occurs in CT VII, 443a, in the forms rn ~.z BIBo, m ~ ~ ~ nwJ.z.
Journal ArticleDOI
JAGUAR: a fully pipelined VLSI architecture for JPEG image compression standard
TL;DR: A fully pipelined single chip VLSI architecture for implementing the JPEG baseline image compression standard that exploits the principles of pipelining and parallelism to the maximum extent in order to obtain high speed and throughput.
Journal ArticleDOI
On the realization of discrete cosine transform using the distributed arithmetic
Yuk-Hee Chan,Wan-Chi Siu +1 more
TL;DR: An efficient unified DCT/IDCT chip is proposed to demonstrate the superiority of the formulation and can easily meet the speed requirement of 14.3 MHz real-time operation with the current 2 mu m CMOS technology.