An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a cavity below the major surface; a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; a Ge-containing dielectric layer over the strained material; and a metal layer over the Ge-containing dielectric layer.

Contact Structure of Semiconductor Device

A 1.5-V 100-mA capacitor-free CMOS low-dropout regulator (LDO) for system-on-chip applications to reduce board space and external pins is presented. By utilizing damping-factor-control frequency compensation on the advanced LDO structure, the proposed LDO provides high stability, as well as fast line and load transient responses, even in capacitor-free operation. The proposed LDO has been implemented in a commercial 0.6-/spl mu/m CMOS technology, and the active chip area is 568 /spl mu/m/spl times/541 /spl mu/m. The total error of the output voltage due to line and load variations is less than /spl plusmn/0.25%, and the temperature coefficient is 38 ppm//spl deg/C. Moreover, the output voltage can recover within 2 /spl mu/s for full load-current changes. The power-supply rejection ratio at 1 MHz is -30 dB, and the output noise spectral densities at 100 Hz and 100 kHz are 1.8 and 0.38 /spl mu/V//spl radic/Hz, respectively.

A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation

Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena.

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Analog circuits in ultra-deep-submicron CMOS

In this paper, the state of the art in ultra-low power (ULP) VLSI design is presented within a unitary framework for the first time. A few general principles are first introduced to gain an insight into the design issues and the approaches that are specific to ULP systems, as well as to better understand the challenges that have to be faced in the foreseeable future. Intuitive understanding is accompanied by rigorous analysis for each key concept. The analysis ranges from the circuit to the micro-architectural level, and reference is given to process, physical and system levels when necessary. Among the main goals of this paper, it is shown that many paradigms and approaches borrowed from traditional above-threshold low-power VLSI design are actually incorrect. Accordingly, common misconceptions in the ULP domain are debunked and replaced with technically sound explanations.

Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial

Techniques are presented for making transversal filters using charge-coupled devices and bucket-brigade devices. In a CCD transversal filter, the delayed signals are sampled by measuring the current flowing the clock lines during transfer, and the sampled signals are weighted by a split electrode technique. In a BBD transversal filter, the delayed signals are `tapped' with a source follower whose load determines the weighting coefficient. Examples are given of CCD and BBD filters that are `matched' to particular signalling waveforms, and the limitations of charge-transfer devices in matched filtering applications are discussed. Finally, the application of CTD transversal filters to other signal processing functions is discussed.

Transversal filtering using charge-transfer devices

Internet electronic products have requirements different from those of personal computers (PCs). The increasing importance of Internet electronics is driving changes in development of IC technology. One important characteristic of the Internet Age is computational disaggregation. Whereas, over the past 20 years, PCs have been characterized by ever-increasing computation capabilities, emerging Internet electronic products are characterized by sufficient computation to achieve the function in a small, often portable, form factor. The imperative for lower cost, which enables penetration into mass markets, is a second area where Internet electronic products differ from PCs. Disaggregation and cost requirements are driving an unprecedented degree of system-on-a-chip (SoC) integration. In the Internet Age, SoC integration means more than integrating different digital cores. It also means integrating functions that are realized today in different technologies: logic, memory, analog, power management, passives and radio or wireline driver, depending on the product. Because SoC integration is motivated primarily by cost, diverse functions must be integrated together in standard CMOS with minimal cost addition. Cost-effective embedded memory technology also needs to be developed. Current examples of SoC integration include cell phones, cable/DSL modems, and Internet audio. These representative examples, together with others, are driving changes in the way ICs are developed. In the latter half of the decade, it is likely that SoC integration will expand to include MEMS, microphotonics, and on-chip energy sources. Moore's Law scaling will continue at least through the end of this decade, but SoC integration will become an increasingly important technology imperative for continued cost reduction throughout the Internet Age.

Technology in the internet age

The most important characteristic of a charge-coupled device is its charge transfer efficiency (CTE). There are three basic types of loss which degrade CTE: fixed loss, proportional loss, and nonlinear loss. Examples are given of each type of loss and techniques for measurement of all three types of loss are described. A method of determining the minimum fat zero which eliminates fixed loss is shown and an experiment is presented which confirms that fixed loss due to surface states can be completely eliminated by the use of a fat zero. The effect of interelectrode gaps on CTE is discussed in detail. A nonlinear loss model is used to describe the dispersion due to barriers in the gaps and the very detrimental effect of wells in the gap region is shown. The techniques presented in the analysis of these losses are very general and can be used whenever a detailed description of the transfer loss mechanism is required.

Experimental characterization of transfer Efficiency in charge-coupled devices

Processors for next generation mobile devices will need to operate across a wide supply voltage range in order to support both high performance and high power efficiency modes of operation. However, the effects of local transistor threshold (VT) variation, already a significant issue in today's advanced process technologies, and further exacerbated at low voltages, complicate the task of designing reliable, manufacturable systems for ultra-low voltage operation. In this paper, we describe a 4-issue VLIW DSP system-on-chip (SoC), which operates at voltages from 1.0 V down to 0.6 V. The SoC was implemented in 28 nm CMOS, using a cell library and SRAMs optimized for both high-speed and low-voltage operating points. A new statistical static timing analysis (SSTA) methodology was also used on this design, in order to more accurately model the effects of local VT variation and achieve a reliable design with minimal pessimism.

A 28 nm 0.6 V Low Power DSP for Mobile Applications

System on a Chip (SOC) integration is being driven by the need for cost reduction in many applications such as wireless cell phones, mass storage, DSL modems, cable modems, short distance wireless, and digital still camera This paper discusses the device issues with the integration of analog and RF functions together with deep submicron digital CMOS

Dennis D. Buss

Papers

Transversal filtering using charge-transfer devices

Technology in the internet age

Experimental characterization of transfer Efficiency in charge-coupled devices

A 28 nm 0.6 V Low Power DSP for Mobile Applications

Device issues in the integration of analog/RF functions in deep submicron digital CMOS