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Derek E. Pappas

Researcher at Nvidia

Publications -  14
Citations -  376

Derek E. Pappas is an academic researcher from Nvidia. The author has contributed to research in topics: Frame (networking) & Block (data storage). The author has an hindex of 8, co-authored 14 publications receiving 376 citations. Previous affiliations of Derek E. Pappas include Intel & Sun Microsystems.

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Patent

Method and apparatus for simulation system compiler

TL;DR: In this article, a method for compiling a cycle-based design involves generating a parsed cyclebased design from the original design, elaborating the parsed cycle based design to an annotated syntax tree, translating the annotated syntactic tree to an intermediate form, and converting the intermediate form to an executable form.
Patent

Method and apparatus for cycle-based computation

TL;DR: In this article, a cycle-based computer system for cycle-aware computation includes a processor array, a translation component adapted to translate a cyclebased design, a host computer operatively connected to the processor array and to the translation component, a data connection component interconnecting a plurality of members of the processor arrays using static routing, a synchronization component enabling known timing relationships among the plurality of member of processors, and an access component adapts to access a portion of a state of the processors.
Patent

Structured and Social Data Aggregator

TL;DR: In this paper, a product information crawler conveys captured web pages to a structured data extractor, which extracts product information and processed social network information to an information aggregator, which merges the information and stores it in a data store that can be queried by a user.
Patent

Method and apparatus for controlling a massively parallel processing environment

TL;DR: In this article, a method for controlling a processor array by a host computer involves creating a graph of a plurality of nodes using a data connection component, configuring a broadcast tree from a spanning tree of the graph, propagating a first command from the host computer to a member of the processor array using the broadcast tree, and transmitting a response from the node to the node using the reply tree.
Patent

Reservation station with a pseudo-FIFO circuit for scheduling dispatch of instructions

TL;DR: In this article, a reservation station includes a memory array in which micro-operations are stored at entry locations with an age representing a temporal ordering, and control circuitry resets the age of a new micro-operation, and increments the ages of previously stored microoperations, when an entry is written into the array.