The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.

Apparatuses and methods for performing logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.

Apparatuses and methods for performing compare operations using sensing circuitry

Examples of the present disclosure provide apparatuses and methods for performing division operations in a memory. An example apparatus comprises a first address space comprising a first number of memory cells coupled to a sense line and to a first number of select lines wherein the first address space stores a dividend value. A second address space comprises a second number of memory cells coupled to the sense line and to a second number of select lines wherein the second address space stores a divisor value. A third address space comprises a third number of memory cells coupled to the sense line and to a third number of select lines wherein the third address space stores a remainder value. Sensing circuitry can be configured to receive the dividend value and the divisor value, divide the dividend value by the divisor value, and store a remainder result in the third number of memory cells.

Division operations for memory

A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime system enables users to leverage the computational power of parallel-processing computer systems to accelerate/optimize numeric and array-intensive computations in their application programs. This enables greatly increased performance of high-performance computing (HPC) applications.

Systems and methods for dynamically choosing a processing element for a compute kernel

Multi-Thread Runtime System

A method for compiling a cycle-based design involves generating a parsed cycle-based design from the cycle-based design, elaborating the parsed cycle-based design to an annotated syntax tree, translating the annotated syntax tree to an intermediate form, and converting the intermediate form to an executable form.

Method and apparatus for simulation system compiler

A method for compiling a logic design includes inputting a logic design and an input file into a plurality of compilers, respectively, where the logic design comprises a plurality of modules, compiling separately the plurality of modules into a plurality of object files, and linking the plurality of object files to execute the logic design.

System & method of linking separately compiled simulations

A dynamic down cast or cross cast is performed at run time within an object-oriented programming language such as C++. The compiler generates data structures during a compile; at run time a routine in the language support library accesses the generated data structures in order to perform the dynamic cast. Class structure information is provided in a size that varies linearly as the total number of classes in the class hierarchy. Cryptographic hashing of class names is used to provide uniqueness. The dynamic cast addresses complications in C++ due to "virtual" and "nonvirtual" inheritance. A run time type identification (RTTI) data structure is created at compile time. An offset within an object description is calculated for each sub-object of the object. Those virtual base classes that are duplicates are skipped producing a data structure that may be searched linearly as the number of classes in the hierarchy. An identifier for each sub-object is stored in the data structure along with its offset. Each virtual table also stores the offset of its corresponding sub-object. A cast operation is performed at run time using the RTTI data structure. The static type object pointer is used to access the object through a particular sub-object. The virtual table associated with the sub-object is used to access the RTTI data structure. The data structure is searched for the target type, and the offset associated with the target type is combined with the offset from the virtual table to adjust the object pointer to cast it to the target type.

Determining the actual class of an object at run time

Improved techniques for reducing the time and cost associated with producing compiler products are disclosed. A programming system including an enhanced compiler suitable for compilation of source programs is disclosed. The enhanced compiler can be used to compile source programs so that template (or generic) instances already available from the libraries are not recreated. The enhanced compiler can efficiently compile a request to create an instance by determining whether the instance is already available in one of the libraries. If the instance is already available from one of the libraries, the instance need not be created. In comparison with conventional models, the enhanced compiler can access libraries directly without requiring a significant amount of preparatory work and/or costly operations such as preparation of options files and transformation of instance names to linker symbol names. As a result, the enhanced compiler is more efficient (faster) than convention compilers.

Method and apparatus for compiling source programs using one or more libraries

A method involves building an intermediate form data flow graph (IFgraph) from an intermediate form data flow tree (IFtree) associated with the logic design, partitioning the IFgraph across at least three levels of granularity to obtain a partitioned IFgraph, wherein partitioning the IFgraph involves balancing a set of nodes of the IFgraph into a first subset and a second subset, wherein each of the first subset and second subset are within a predefined constraint of the cycle-based system, and wherein the balancing is performed on at least one of the levels of granularity, and rewriting the IFtree based on the partitioned IFgraph.

Michael S. Ball

Papers

Method and apparatus for simulation system compiler

System & method of linking separately compiled simulations

Determining the actual class of an object at run time

Method and apparatus for compiling source programs using one or more libraries

Partitioning for a massively parallel simulation system