A
Ankur Narang
Researcher at IBM
Publications - 57
Citations - 1032
Ankur Narang is an academic researcher from IBM. The author has contributed to research in topics: Scalability & Scheduling (computing). The author has an hindex of 13, co-authored 57 publications receiving 1011 citations. Previous affiliations of Ankur Narang include Sun Microsystems & Post Graduate Institute of Medical Education and Research.
Papers
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Patent
Method and apparatus for simulation system compiler
Jeffrey M. Broughton,Liang T. Chen,William K. Lam,Derek E. Pappas,Ihao Chen,Thomas M. McWilliams,Ankur Narang,Jeffrey B. Rubin,Earl T. Cohen,Michael W. Parkin,Ashley Saulsbury,Michael S. Ball +11 more
TL;DR: In this article, a method for compiling a cycle-based design involves generating a parsed cyclebased design from the original design, elaborating the parsed cycle based design to an annotated syntax tree, translating the annotated syntactic tree to an intermediate form, and converting the intermediate form to an executable form.
Patent
Parallel data redundancy removal
TL;DR: In this paper, a method, system, and computer usable program product for parallel data redundancy removal are provided in the illustrative embodiments, where a plurality of values is computed for a record in the plurality of records stored in a storage device, and a determination is made whether each value distributed to the corresponding queues for the record is indicated by a corresponding value in the Bloom filter.
Patent
System & method of linking separately compiled simulations
TL;DR: In this article, a method for compiling a logic design is presented, where the logic design comprises a plurality of modules, compiling separately the plurality of module files into object files, and linking the plurality files to execute the logic.
Patent
Constraint-based global router for routing high performance designs
TL;DR: In this paper, a global routing solution is provided to a detailed router, which completes the routing for the design of integrated circuits, based on constraints being satisfied for the entire design.
Patent
Assigning Threads and Data of Computer Program within Processor Having Hardware Locality Groups
Ankur Narang,Ravi Kothari +1 more
TL;DR: In this paper, a computer program having threads and data is assigned to a processor having a processor cores and memory organized over hardware locality groups, and the computer program is profiled to generate a data thread interaction graph (DTIG) representing the computer programs.