Showing papers by "Dinesh K. Sharma published in 2006"

Interface design for rationally clocked GALS systems

Abstract: We investigate the problem of designing interface circuits for rationally clocked modules in GALS systems. As a key contribution, we show that knowledge of flow-control protocols can be used to significantly optimize synchronization mechanisms. We present delay-augmented netcharts as a formalism for representing communication protocols and describe techniques to analyze them. We use the results of our analysis to design a simple yet generic interface that is optimized for the given protocol and is free from synchronization failures. We show by means of case studies the inherent advantages of our methodology over an existing solution technique.

Reasoning about synchronization in GALS systems

Abstract: Correct design of interface circuits is crucial for the development of System-on-Chips (SoC) using off-the-shelf IP cores. For correct operation, an interface circuit must meet strict synchronization timing constraints, and also respect sequencing constraints between events dictated by interfacing protocols and rational clock relations. In this paper, we propose a technique for automatically analyzing the interaction between independently specified synchronization constraints and sequencing constraints between events. We show how this analysis can be used to derive delay constraints for correct operation of interface circuits in a GALS system. Our methodology allows an SoC designer to mix and match different interfacing protocols, rational clock relations and synchronization constraints for communication between a pair of modules, and automatically explore their implications on correct interface circuit design.

Impact of Process variations on Leakage Power in CMOS Circuits in Nano Era (Invited paper)

Abstract: In sub 90 nm CMOS technology the process variations seriously affect the performance specification for leakage power and delay. In this paper, we have analyzed the techniques to improve the design quality for power and performance sensitivity to process variations. At gate level forced stacking not only reduces leakage but also improves the robustness of the gate to process variations. Logic style level the variation of leakage current with the Vth variation for various logic styles is studied

Wireless E-Jacket for Multiparameter Biophysical Monitoring and Telemedicine Applications

Abstract: A widespread requirement exists for a low cost and reliable health monitor in the clinical as well as home environment. The e-jacket presented here is an example of a smart clothing system with multiple bioparameter acquisition of electrocardiogram (ECG), pulse oximetry, body motion/tilt and skin temperature. The battery operated circuit has an integrated graphic liquid crystal display (LCD) screen and a 2.4 GHz wireless link. An RS232 interface provides a plug-in port for easy accessibility to remote telemedicine applications. The system incorporates an efficient ARM7 microcontroller to coordinate a list of software tasks with associated time stamp. Comfort analysis and reliability aspects have been carefully studied along with intelligent power conservation schemes. A low cost and reliable tele-medical network is proposed using an innovative e-textile solution.

A novel low power multilevel current mode interconnect system

Abstract: We propose circuits for low power, high throughput multilevel current mode signaling using 2 bit simultaneous data transfer. A novel design of the receiver for very low line voltage swings is discussed. The technique involves matching the receiver impedance to the line impedance thereby reducing the ringing on the wire. Simulation results show up to 50% reduction in latency and up to 100 times reduction in power over voltage mode buffer insertion techniques. We also show that the delays through this system are largely independent of the interconnect lengths. Data rates of up to 1Gb/s have been obtained. A power consumption model is derived for the system which matches the simulation results to within 5%.

A Wideband Low Power VCO for IEEE 802.11a

Abstract: A fully integrated wide tuning range and low power VCO, using a new combination of accumulation-mode (A-MOS) varactors in LC tank, has been presented. The VCO is implemented in 0.25-mum technology and has a tuning range of 1.35GHz, from 4.93GHz to 6.28GHz. It consumes 1.8mA of current from a 2.5V supply and achieves low phase noise of -116.1dBc/Hz @1MHz offset from 5.7GHz carrier. The VCO designed has a tuning range, which covers all of the three bands of IEEE WLAN 802.11a standard and satisfies the phase noise specifications