In this paper we have designed an energy efficient multiplier using Nikhilam Navatashcaramam Dashatah Vedic technique. Vedic mathematics consists of 16 sutras and these sutras were used by our ancient scholars for doing there calculation faster, when there were no computers and calculators. Nikhilam Navatasaman is a Sanskrit word which menas “all from 9 and the last from 10”. In today’s work the demand is high speed, efficiency and should take lesser time. Appling these Vedic techniques reduces the system complexity, execution time, area, power and is stable and hence is efficient method. In this paper we have designed an energy efficient multiplier that consists of three inputs and one output. The temperature has been kept constant that is 25 degree Celsius. Airflow has been kept 250 LFM and medium Heat sink. IO Standards has been varied in order to achieve an energy efficient device. In this paper we have taken HSTL (High Speed Transceiver Logic) IOSTANDARD. In order to achieve speed and high performance in addition to energy efficiency, HSTL IO standard is used. HSTL family consists of HSTL _I, HSTL_II, HSTL_I_18 and HSTL_II_18, HSTL_I_12 and the analysis has been done on these IO standards. Frequency scaling is one of the best energy efficient techniques for FPGA based VLSI design and is used in this paper. At the end we can conclude that we can conclude that there is 23-40% saving of total power dissipation by using SSTL IO standard at 25 degree Celsius. The main reason for power consumption is leakage power at different IO Standards and at different frequencies. In this research work only FPGA work has been performed not ultra scale FPGA.

HSTL IO Standard Based Energy Efficient Multiplier Design using Nikhilam Navatashcaramam Dashatah on 28nm FPGA

This paper presents design of optimized high speed and low power Vedic multiplier based on Vedic sutra Urdhva Tiryagbhyam. Adiabatic logic is used to reduce the power consumption of Vedic multiplier and its performance is evaluated by comparing it with conventional MOS design. The power consumption of Adiabatic Vedic multiplier is less than power consumed by Vedic multiplier without adiabatic logic is analyzed. The circuit 2×2, 4×4 Vedic multipliers are designed and simulated on 180nm technology using Tanner EDA Tool 13.0.

Implementation of optimized vedic multiplier using CMOS technology

This paper is designed to
introduce new hybrid Vedic algorithm to increase the speed of the multiplier.
This work combines the principles of Nikhilam sutra and Karatsuba algorithm.
Vedic Mathematics is the mathematical system to solve the complex computations
in an easier manner. There are specific sutras to perform multiplication.
Nikhilam sutra is one of the sutra. But this has some limitations. To overcome
the limitations, this sutra is combined with Karatsuba algorithm. High speed
devices are required for high speed applications with compact size. Normally
multipliers require more power for its computation. In this paper, new
multiplication algorithm for the multiplication of binary numbers is proposed
based on Vedic Mathematics. The novel portion in the algorithm is found to be
in the calculation of remainder using complement method. The size of the
remainder is always set as N - 1 bit for any combination of input.
The multiplier structure is designed based on Karatsuba algorithm. Therefore, N × N bit multiplication is done by (N - 1) bit multiplication. Numerical
strength reduction is done through Karatsuba algorithm. The results show that
the reduction in hardware leads to reduction in the delay.

/pdf/implementation-of-n-bit-binary-multiplication-using-n-1-bit-yxraqdcdm9.pdf

Implementation of N-Bit Binary Multiplication Using N - 1 Bit Multiplication Based on Nikhilam Sutra and Karatsuba Principles Using Complement Method

With an ever growing demand for low-power devices, it is a general trend to search for ways to reduce the power consumption of a system. Multipliers are an important requirement in applications linked to Digital Signal Processing, Communication Systems, Optical Computing, Nanotechnology, Low-Power Very Large Scale Integration and Quantum Computing. Conventional mathematics makes multiplication a very long and time consuming process. The use of Vedic mathematics has led to great reduction in the time required for such calculations. The excessive use of Urdhava Tiryakbhyam sutra in multiplication surely proves its effectiveness and simplicity in this domain. This sutra supports the process of pipelining, a method employed in reduction of the power used by a system. Reversible logic has been gaining demand due to its low-power capabilities and is currently being used in many computing applications. The paper proposes two multiplier systems: one design employs the Urdhava Tiryakbhyam sutra along with pipelining and the second uses reversible logic gates into the first design. These proposed systems provide very less delay for result computation and low hardware utilization when compared to non-pipelined Vedic multipliers.

/pdf/reversible-logic-in-pipelined-low-power-vedic-multiplier-4zpkehsf7a.pdf

Reversible logic in pipelined low power vedic multiplier

With the initiation of ancient Vedic mathematics (AVM) concepts, very large-scale integration technique becomes more powerful in developing various VLSI computing systems. In the last decade, people have tried to integrate the Vedic mathematics techniques with the VLSI theory. Hence, analyzing methods, designing and manipulating the performance from circuit- and system-level perspectives become a vital task and challenging too. Performance study of various diverse techniques that are used for developing high-performance VLSI computing systems is the central focus of this paper. This paper provides a comprehensive survey of different designing techniques, complementing the limits of existing reviews in the literature. The survey covers introduction to Vedic methods, motivation toward the work, various designing techniques with their limitations, etc. This paper can be seen as a foremost step to present a state-of-the-art impression of revision work carried in developing high-performance VLSI computing systems.

Developing High-Performance AVM Based VLSI Computing Systems: A Study

With the enrichment of new technology in the fields of VLSI design and communication there is also a demand of high speed and low area. The aim of this paper is to design a multiplier circuit based on Vedic sutras. The algorithms based on conventional mathematics can be optimized and simplified by using Vedic sutras. In this paper we have given the design up to Multipliers based on Vedic multiplication sutra “Urdhva-Tiryakbhyam” the design of 2×2, 4×4 has been designed in DSCH2 and all the outputs have been given. The layout of those circuits has been also generated by Microwind. The internal circuit diagram of all the blocks has been explained The noise, power have been calculated by T-Spice-13 in 45nm Technology. The hardware has also been implemented in XILINX and tested in Basys™2 Spartan-3E FPGA Board.

http://ieeexplore.ieee.org/iel7/6917157/6926115/06926192.pdf

Implementation of optimized high performance 4×4 multiplier using ancient Vedic sutra in 45 nm technology

Digital signal processing (DSP) operations are very important part of engineering as well as medical discipline. Designing of DSP operations have many approaches. For the designing of DSP operations, multiplication plays a important role to perform signal processing operations such as convolution and correlation. The aim of this paper is to design a multiplier circuit based on Vedic sutras and method for DSP operations based on ancient Vedic mathematics is contemplated. In this paper, we have given the design up to multipliers based on Vedic multiplication sutra ‘Urdhva-Tiryakbhyam’ the design of 4 × 4 has been sketched in DSCH2 and all the outputs have been given. The layout of those circuits has also been generated by Microwind. The internal circuit diagram of all the blocks has been explained. The noise power have been calculated by T-Spice-13 in 45 nm Technology. This algorithm is implemented in MATLAB and also compared with the inbuilt functions in MATLAB.

Implementation of High Performance Vedic Multiplier and Design of DSP Operations Using Vedic Sutra

A central processing unit needs a considerable amount of processing time in performing logical operations, arithmetic operations, particularly multiplication operations. Multiplication is one of the arithmetic operations which require substantially more number of hardware resources and processing time than addition and subtraction. A multiplier is consist of mainly AND gates and Full Adders. Now a day’s resources are an important factor in case of any design. Any design must have less number of resources as well as it must be power efficient, noise immune. This paper presents a new high speed and Power efficient 4-bit Braun Multiplier and 4 bit Baugh Wooley Multiplier with less number of CMOS transistors. The circuit diagram is tested in 0.045μm i.e. 45 nm Technology. All the designs have been designed in DSCH2. Also Noise, Power and Delay have been calculated in Tanner Spice-13 in 45nm Technology. Keywords— Braun Multiplier Baugh Wooley Multiplier, TSpice, DSCH2,

/pdf/comparative-analysis-of-noise-power-and-area-of-4-bit-braun-2uxp0hvw13.pdf

Comparative Analysis of Noise, Power and Area of 4 Bit Braun Multiplier and Baugh Wooley Multiplier with Minimum Number of Transistors in 45nm Technology

Diptendu Kumar Kundu

Papers

Implementation of optimized high performance 4×4 multiplier using ancient Vedic sutra in 45 nm technology

Implementation of High Performance Vedic Multiplier and Design of DSP Operations Using Vedic Sutra

Comparative Analysis of Noise, Power and Area of 4 Bit Braun Multiplier and Baugh Wooley Multiplier with Minimum Number of Transistors in 45nm Technology